Details
| Originalsprache | Englisch |
|---|---|
| Seiten (von - bis) | 19-34 |
| Seitenumfang | 16 |
| Fachzeitschrift | Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology |
| Jahrgang | 40 |
| Ausgabenummer | 1 |
| Publikationsstatus | Veröffentlicht - 1 Mai 2005 |
| Extern publiziert | Ja |
Abstract
The exploration of the design space for heterogeneous Systems on Chip (SoC) becomes more and more important. As modern SoCs include a variety of different architecture blocks ensuring flexibility as well as highest performance it is mandatory to prune the design space in an early stage of the design process in order to achieve short innovation cycles for new products. Thus the goal of this work is to provide estimations of implementation specific parameters like throughput rate power dissipation and silicon area by means of cost functions featuring reasonable accuracy at low modeling effort. A model based exploration strategy supporting the design flow for heterogeneous SoCs is presented. In order to demonstrate the feasibility of this exploration strategy in a first step implementation cost parameters are provided for a variety of basic operations frequently required in digital signal processing which were implemented on discrete components like DSPs FPGAs or dedicated ASICs. These implementation parameters serve as a basis for deriving cost models for the design space exploration concept.
ASJC Scopus Sachgebiete
- Informatik (insg.)
- Signalverarbeitung
- Informatik (insg.)
- Information systems
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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in: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, Jahrgang 40, Nr. 1, 01.05.2005, S. 19-34.
Publikation: Beitrag in Fachzeitschrift › Artikel › Forschung › Peer-Review
}
TY - JOUR
T1 - Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip
AU - Blume, H.
AU - Feldkaemper, H. T.
AU - Noll, T.
PY - 2005/5/1
Y1 - 2005/5/1
N2 - The exploration of the design space for heterogeneous Systems on Chip (SoC) becomes more and more important. As modern SoCs include a variety of different architecture blocks ensuring flexibility as well as highest performance it is mandatory to prune the design space in an early stage of the design process in order to achieve short innovation cycles for new products. Thus the goal of this work is to provide estimations of implementation specific parameters like throughput rate power dissipation and silicon area by means of cost functions featuring reasonable accuracy at low modeling effort. A model based exploration strategy supporting the design flow for heterogeneous SoCs is presented. In order to demonstrate the feasibility of this exploration strategy in a first step implementation cost parameters are provided for a variety of basic operations frequently required in digital signal processing which were implemented on discrete components like DSPs FPGAs or dedicated ASICs. These implementation parameters serve as a basis for deriving cost models for the design space exploration concept.
AB - The exploration of the design space for heterogeneous Systems on Chip (SoC) becomes more and more important. As modern SoCs include a variety of different architecture blocks ensuring flexibility as well as highest performance it is mandatory to prune the design space in an early stage of the design process in order to achieve short innovation cycles for new products. Thus the goal of this work is to provide estimations of implementation specific parameters like throughput rate power dissipation and silicon area by means of cost functions featuring reasonable accuracy at low modeling effort. A model based exploration strategy supporting the design flow for heterogeneous SoCs is presented. In order to demonstrate the feasibility of this exploration strategy in a first step implementation cost parameters are provided for a variety of basic operations frequently required in digital signal processing which were implemented on discrete components like DSPs FPGAs or dedicated ASICs. These implementation parameters serve as a basis for deriving cost models for the design space exploration concept.
KW - Cost models
KW - Design space exploration
KW - Heterogeneous systems on chip
KW - Partitioning and mapping
KW - Reconfigurable platforms
UR - http://www.scopus.com/inward/record.url?scp=14844356100&partnerID=8YFLogxK
U2 - 10.1007/s11265-005-4936-4
DO - 10.1007/s11265-005-4936-4
M3 - Article
AN - SCOPUS:14844356100
VL - 40
SP - 19
EP - 34
JO - Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
JF - Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology
SN - 1387-5485
IS - 1
ER -