Memory organization of a single-chip video signal processing system with embedded DRAM

Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review

Autoren

  • Joerg Hilgenstock
  • Klaus Herrmann
  • Peter Pirsch

Organisationseinheiten

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Details

OriginalspracheEnglisch
Titel des SammelwerksProceedings of the IEEE Great Lakes Symposium on VLSI
Seiten42-45
Seitenumfang4
PublikationsstatusVeröffentlicht - 1999
Veranstaltung1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99) - Ann Arbor, MI, USA
Dauer: 4 März 1999 → 6 März 1999

Publikationsreihe

NameProceedings of the IEEE Great Lakes Symposium on VLSI
ISSN (Print)1066-1395

Abstract

A programmable single-chip multiprocessor system for video coding applications has been developed. It integrates four processing elements, on-chip DRAM, and application-specific interfaces. The integrated DRAM is primarily used as frame buffer and makes external memory for most applications obsolete. For fast access to local data segments also static RAM is integrated in each processing element.

ASJC Scopus Sachgebiete

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Memory organization of a single-chip video signal processing system with embedded DRAM. / Hilgenstock, Joerg; Herrmann, Klaus; Pirsch, Peter.
Proceedings of the IEEE Great Lakes Symposium on VLSI. 1999. S. 42-45 (Proceedings of the IEEE Great Lakes Symposium on VLSI).

Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review

Hilgenstock, J, Herrmann, K & Pirsch, P 1999, Memory organization of a single-chip video signal processing system with embedded DRAM. in Proceedings of the IEEE Great Lakes Symposium on VLSI. Proceedings of the IEEE Great Lakes Symposium on VLSI, S. 42-45, 1999 9th Great Lakes Symposium on VLSI (GLSVLSI '99), Ann Arbor, MI, USA, 4 März 1999.
Hilgenstock, J., Herrmann, K., & Pirsch, P. (1999). Memory organization of a single-chip video signal processing system with embedded DRAM. In Proceedings of the IEEE Great Lakes Symposium on VLSI (S. 42-45). (Proceedings of the IEEE Great Lakes Symposium on VLSI).
Hilgenstock J, Herrmann K, Pirsch P. Memory organization of a single-chip video signal processing system with embedded DRAM. in Proceedings of the IEEE Great Lakes Symposium on VLSI. 1999. S. 42-45. (Proceedings of the IEEE Great Lakes Symposium on VLSI).
Hilgenstock, Joerg ; Herrmann, Klaus ; Pirsch, Peter. / Memory organization of a single-chip video signal processing system with embedded DRAM. Proceedings of the IEEE Great Lakes Symposium on VLSI. 1999. S. 42-45 (Proceedings of the IEEE Great Lakes Symposium on VLSI).
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