Details
| Originalsprache | Englisch |
|---|---|
| Seiten (von - bis) | 1090-1095 |
| Seitenumfang | 6 |
| Fachzeitschrift | Microelectronics reliability |
| Jahrgang | 49 |
| Ausgabenummer | 9-11 |
| Publikationsstatus | Veröffentlicht - Sept. 2009 |
Abstract
In ULSI multilevel metallizations the via bottom is the main region for the appearance of local stress. This local stress can lead to fractures or porous spots. Out of this concerning the local stress distribution the via bottom region has to be investigated. Due to various technological processes the via shape especially the via bottom geometries are different. In this paper FE-Simulations with respect to the different via bottom geometries and different temperatures of the process steps will be presented. The best via bottom geometry is figured out. The submodeling technique in ANSYS® is used for these investigations for reduction of simulation time and precise results. The thickness of the barrier has also an influence on the mechanical stress and will be also investigated.
ASJC Scopus Sachgebiete
- Werkstoffwissenschaften (insg.)
- Elektronische, optische und magnetische Materialien
- Physik und Astronomie (insg.)
- Atom- und Molekularphysik sowie Optik
- Ingenieurwesen (insg.)
- Sicherheit, Risiko, Zuverlässigkeit und Qualität
- Physik und Astronomie (insg.)
- Physik der kondensierten Materie
- Werkstoffwissenschaften (insg.)
- Oberflächen, Beschichtungen und Folien
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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in: Microelectronics reliability, Jahrgang 49, Nr. 9-11, 09.2009, S. 1090-1095.
Publikation: Beitrag in Fachzeitschrift › Artikel › Forschung › Peer-Review
}
TY - JOUR
T1 - Investigation of stress distribution in via bottom of Cu-via structures with different via form by means of submodeling
AU - Ciptokusumo, Johar
AU - Weide-Zaage, Kirsten
AU - Aubel, Oliver
N1 - Copyright: Copyright 2009 Elsevier B.V., All rights reserved.
PY - 2009/9
Y1 - 2009/9
N2 - In ULSI multilevel metallizations the via bottom is the main region for the appearance of local stress. This local stress can lead to fractures or porous spots. Out of this concerning the local stress distribution the via bottom region has to be investigated. Due to various technological processes the via shape especially the via bottom geometries are different. In this paper FE-Simulations with respect to the different via bottom geometries and different temperatures of the process steps will be presented. The best via bottom geometry is figured out. The submodeling technique in ANSYS® is used for these investigations for reduction of simulation time and precise results. The thickness of the barrier has also an influence on the mechanical stress and will be also investigated.
AB - In ULSI multilevel metallizations the via bottom is the main region for the appearance of local stress. This local stress can lead to fractures or porous spots. Out of this concerning the local stress distribution the via bottom region has to be investigated. Due to various technological processes the via shape especially the via bottom geometries are different. In this paper FE-Simulations with respect to the different via bottom geometries and different temperatures of the process steps will be presented. The best via bottom geometry is figured out. The submodeling technique in ANSYS® is used for these investigations for reduction of simulation time and precise results. The thickness of the barrier has also an influence on the mechanical stress and will be also investigated.
UR - http://www.scopus.com/inward/record.url?scp=69249206570&partnerID=8YFLogxK
U2 - 10.1016/j.microrel.2009.07.043
DO - 10.1016/j.microrel.2009.07.043
M3 - Article
AN - SCOPUS:69249206570
VL - 49
SP - 1090
EP - 1095
JO - Microelectronics reliability
JF - Microelectronics reliability
SN - 0026-2714
IS - 9-11
ER -