Implementation of real-time SAR-systems with a high performance digital signal processor

Publikation: Beitrag in FachzeitschriftKonferenzaufsatz in FachzeitschriftForschungPeer-Review

Autorschaft

  • H. Kloos
  • J. P. Wittenburg
  • W. Hinrichs
  • H. Lieske
  • P. Pirsch
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Details

OriginalspracheEnglisch
Seiten (von - bis)343-347
Seitenumfang5
FachzeitschriftProceedings of SPIE - The International Society for Optical Engineering
Jahrgang3871
PublikationsstatusVeröffentlicht - 1999
Veranstaltung1999 Image and Signal Processing for Remote Sensing V - Florence, Italy
Dauer: 22 Sept. 199924 Sept. 1999

Abstract

Real-time Synthetic Aperture Radar (SAR) image synthesis is one of the major problems to solve in the future. To achieve a fully synthesized SAR image, the raw signal must be filtered with a 2-dimensional function representing the system transfer function. These filtering operations are usually processed by multiplication in frequency domain. Therefore, the Fast Fourier Transform (FFT) used for transformation to / from frequency domain is the predominant algorithm in terms of processing power for SAR image synthesis. The presented HiPAR-DSP is a programmable architecture, which is optimized for FFT-dominated applications like SAR image processing. To provide the high requested processing power for these task, the HiPAR-DSP has an array of 4 (HiPAR-DSP4) respectively 16 (HiPAR-DSP16) parallel processing units (datapaths) which is controlled by an single RISC Controller. For data exchange between the processing units there is a shared memory which allows the concurrent access from all processing units in a single clock cycle. So the HiPAR-DSP16 performs a complex FFT with 1024 Samples in 32 μs. For the implemented SAR-Processing task, the Range Compression with 4096 complex samples per line we achieve a real-time performance of nearly 1500 rangelines/s.

ASJC Scopus Sachgebiete

Zitieren

Implementation of real-time SAR-systems with a high performance digital signal processor. / Kloos, H.; Wittenburg, J. P.; Hinrichs, W. et al.
in: Proceedings of SPIE - The International Society for Optical Engineering, Jahrgang 3871, 1999, S. 343-347.

Publikation: Beitrag in FachzeitschriftKonferenzaufsatz in FachzeitschriftForschungPeer-Review

Kloos, H, Wittenburg, JP, Hinrichs, W, Lieske, H & Pirsch, P 1999, 'Implementation of real-time SAR-systems with a high performance digital signal processor', Proceedings of SPIE - The International Society for Optical Engineering, Jg. 3871, S. 343-347.
Kloos, H., Wittenburg, J. P., Hinrichs, W., Lieske, H., & Pirsch, P. (1999). Implementation of real-time SAR-systems with a high performance digital signal processor. Proceedings of SPIE - The International Society for Optical Engineering, 3871, 343-347.
Kloos H, Wittenburg JP, Hinrichs W, Lieske H, Pirsch P. Implementation of real-time SAR-systems with a high performance digital signal processor. Proceedings of SPIE - The International Society for Optical Engineering. 1999;3871:343-347.
Kloos, H. ; Wittenburg, J. P. ; Hinrichs, W. et al. / Implementation of real-time SAR-systems with a high performance digital signal processor. in: Proceedings of SPIE - The International Society for Optical Engineering. 1999 ; Jahrgang 3871. S. 343-347.
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AU - Kloos, H.

AU - Wittenburg, J. P.

AU - Hinrichs, W.

AU - Lieske, H.

AU - Pirsch, P.

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N2 - Real-time Synthetic Aperture Radar (SAR) image synthesis is one of the major problems to solve in the future. To achieve a fully synthesized SAR image, the raw signal must be filtered with a 2-dimensional function representing the system transfer function. These filtering operations are usually processed by multiplication in frequency domain. Therefore, the Fast Fourier Transform (FFT) used for transformation to / from frequency domain is the predominant algorithm in terms of processing power for SAR image synthesis. The presented HiPAR-DSP is a programmable architecture, which is optimized for FFT-dominated applications like SAR image processing. To provide the high requested processing power for these task, the HiPAR-DSP has an array of 4 (HiPAR-DSP4) respectively 16 (HiPAR-DSP16) parallel processing units (datapaths) which is controlled by an single RISC Controller. For data exchange between the processing units there is a shared memory which allows the concurrent access from all processing units in a single clock cycle. So the HiPAR-DSP16 performs a complex FFT with 1024 Samples in 32 μs. For the implemented SAR-Processing task, the Range Compression with 4096 complex samples per line we achieve a real-time performance of nearly 1500 rangelines/s.

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