Details
| Originalsprache | Englisch |
|---|---|
| Seiten (von - bis) | 105-113 |
| Seitenumfang | 9 |
| Fachzeitschrift | Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems |
| Jahrgang | Part F5373300 |
| Publikationsstatus | Veröffentlicht - 2000 |
| Veranstaltung | The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Yamanashi, Jpn Dauer: 25 Okt. 2000 → 27 Okt. 2000 |
Abstract
An architecture of a multiprocessor coding system suitable for large area integration has been developed. Application field is video coding according to the international standards ISO MPEG-2 and ITU-T H. 263 or similar methods. It is based on processor nodes, which consist of a 1.9 GOPS video signal processor AxPe, 4 MBit of embedded DRAM, and digital video interfaces for data input and output as well as for inter-processor communication. Four of these processor nodes can be fabricated with a single mask set on a 0.25 μm CMOS circuit of 2×2 cm2, which is called AxPe subsystem. By overlapping manufacturing and cutting out of 2×2 of AxPe subsystems afterwards, a large area integrated circuit (LAIC) with 16 processor nodes can be realized. The upper metal layers of each AxPe subsystem contains connection structures at the chip boundaries for this purpose. Redundancy techniques ensure the functionality of the LAIC even in the case of defect processor nodes.
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in: Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, Jahrgang Part F5373300, 2000, S. 105-113.
Publikation: Beitrag in Fachzeitschrift › Konferenzaufsatz in Fachzeitschrift › Forschung › Peer-Review
}
TY - JOUR
T1 - Implementation of a Multiprocessor System with Distributed Embedded DRAM on a Large Area Integrated Circuit
AU - Herrmann, Klaus
AU - Moch, Sören
AU - Hilgenstock, Jörg
AU - Pirsch, Peter
N1 - Funding Information: A programmable and monolithic video signal processing system has been developed. It consists of 16 processing nodes and 64 Mbit DRAM as embedded frame memory, which is distributed among the processors. Each processor node consists of an AxPe video signal processor core, embedded frame memory and interfaces for video data input and output. The entire architecture of the multiprocessor system has been adapted for an implementation as large area integrated circuit. Redundancy techniques have been integrated in all levels of the design. A coarse grained structure with identical processor nodes allows, that single processor nodes can be deactivated in the case of defects. All bus systems contain spare lines, so that defect lines can be replaced by laser switches. In the processor nodes all interface modules can cope with long wire delays on the global interconnection bus lines. Furthermore, they work independently of the number of defect processors. The design shows, that with current state of the art manufacturing techniques a multiprocessor system with embedded DRAM can be implemented as a large area integrated circuit. Acknowledgments The authors would like to thank Origin ASIC Support Centre, Hamburg, for the design of the full custom modules and the layout of the chips. This research has been supported by FhG under contract no. T/F41B/T0183/P1307.
PY - 2000
Y1 - 2000
N2 - An architecture of a multiprocessor coding system suitable for large area integration has been developed. Application field is video coding according to the international standards ISO MPEG-2 and ITU-T H. 263 or similar methods. It is based on processor nodes, which consist of a 1.9 GOPS video signal processor AxPe, 4 MBit of embedded DRAM, and digital video interfaces for data input and output as well as for inter-processor communication. Four of these processor nodes can be fabricated with a single mask set on a 0.25 μm CMOS circuit of 2×2 cm2, which is called AxPe subsystem. By overlapping manufacturing and cutting out of 2×2 of AxPe subsystems afterwards, a large area integrated circuit (LAIC) with 16 processor nodes can be realized. The upper metal layers of each AxPe subsystem contains connection structures at the chip boundaries for this purpose. Redundancy techniques ensure the functionality of the LAIC even in the case of defect processor nodes.
AB - An architecture of a multiprocessor coding system suitable for large area integration has been developed. Application field is video coding according to the international standards ISO MPEG-2 and ITU-T H. 263 or similar methods. It is based on processor nodes, which consist of a 1.9 GOPS video signal processor AxPe, 4 MBit of embedded DRAM, and digital video interfaces for data input and output as well as for inter-processor communication. Four of these processor nodes can be fabricated with a single mask set on a 0.25 μm CMOS circuit of 2×2 cm2, which is called AxPe subsystem. By overlapping manufacturing and cutting out of 2×2 of AxPe subsystems afterwards, a large area integrated circuit (LAIC) with 16 processor nodes can be realized. The upper metal layers of each AxPe subsystem contains connection structures at the chip boundaries for this purpose. Redundancy techniques ensure the functionality of the LAIC even in the case of defect processor nodes.
UR - http://www.scopus.com/inward/record.url?scp=0034503005&partnerID=8YFLogxK
U2 - 10.1109/DFTVS.2000.887148
DO - 10.1109/DFTVS.2000.887148
M3 - Conference article
AN - SCOPUS:0034503005
VL - Part F5373300
SP - 105
EP - 113
JO - Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
JF - Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
SN - 1550-5774
T2 - The IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Y2 - 25 October 2000 through 27 October 2000
ER -