Details
| Originalsprache | Englisch |
|---|---|
| Seiten (von - bis) | 271-276 |
| Seitenumfang | 6 |
| Fachzeitschrift | Advances in Radio Science |
| Jahrgang | 3 |
| Publikationsstatus | Veröffentlicht - 12 Mai 2005 |
| Extern publiziert | Ja |
Abstract
One of the most important error correction codes in digital signal processing is the Reed Solomon code. A lot of VLSI implementations have been described in literature. This paper introduces a highly parametrizable RS-decoder for FPGAs. By implementing resource-sharing and by using a fully pipelined multiplier/adder-unit in GF(2m) it was possible to achieve high throughput rates up to 1.3Gbit/s on a standard FPGA, while using only an attractive small amount of logical elements (LE). The implementation, written in a hardware description language (HDL), is based on an inversionless Berlekamp Algorithm (iBA), whose structure leads to a chain of identical processing elements (PE). The critical path of one PE runs only through one adder and one multiplier. A detailed description of a resource-sharing methodology for this Berlekamp Algorithm and the achievable gain are presented in this paper.p/p styleCombining double low line"line-height: 20px;"> The benchmarking for the design was done for different 8bit-codes against state-of-the-art FPGA-solutions and showed a gain of up to a factor of six regarding the AT-product, compared to other implementations.
ASJC Scopus Sachgebiete
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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in: Advances in Radio Science, Jahrgang 3, 12.05.2005, S. 271-276.
Publikation: Beitrag in Fachzeitschrift › Artikel › Forschung › Peer-Review
}
TY - JOUR
T1 - Implementation and modeling of parametrizable high-speed Reed Solomon decoders on FPGAs
AU - Flocke, A.
AU - Blume, H.
AU - Noll, T. G.
PY - 2005/5/12
Y1 - 2005/5/12
N2 - One of the most important error correction codes in digital signal processing is the Reed Solomon code. A lot of VLSI implementations have been described in literature. This paper introduces a highly parametrizable RS-decoder for FPGAs. By implementing resource-sharing and by using a fully pipelined multiplier/adder-unit in GF(2m) it was possible to achieve high throughput rates up to 1.3Gbit/s on a standard FPGA, while using only an attractive small amount of logical elements (LE). The implementation, written in a hardware description language (HDL), is based on an inversionless Berlekamp Algorithm (iBA), whose structure leads to a chain of identical processing elements (PE). The critical path of one PE runs only through one adder and one multiplier. A detailed description of a resource-sharing methodology for this Berlekamp Algorithm and the achievable gain are presented in this paper.p/p styleCombining double low line"line-height: 20px;"> The benchmarking for the design was done for different 8bit-codes against state-of-the-art FPGA-solutions and showed a gain of up to a factor of six regarding the AT-product, compared to other implementations.
AB - One of the most important error correction codes in digital signal processing is the Reed Solomon code. A lot of VLSI implementations have been described in literature. This paper introduces a highly parametrizable RS-decoder for FPGAs. By implementing resource-sharing and by using a fully pipelined multiplier/adder-unit in GF(2m) it was possible to achieve high throughput rates up to 1.3Gbit/s on a standard FPGA, while using only an attractive small amount of logical elements (LE). The implementation, written in a hardware description language (HDL), is based on an inversionless Berlekamp Algorithm (iBA), whose structure leads to a chain of identical processing elements (PE). The critical path of one PE runs only through one adder and one multiplier. A detailed description of a resource-sharing methodology for this Berlekamp Algorithm and the achievable gain are presented in this paper.p/p styleCombining double low line"line-height: 20px;"> The benchmarking for the design was done for different 8bit-codes against state-of-the-art FPGA-solutions and showed a gain of up to a factor of six regarding the AT-product, compared to other implementations.
UR - http://www.scopus.com/inward/record.url?scp=72449182910&partnerID=8YFLogxK
U2 - 10.5194/ars-3-271-2005
DO - 10.5194/ars-3-271-2005
M3 - Article
AN - SCOPUS:72449182910
VL - 3
SP - 271
EP - 276
JO - Advances in Radio Science
JF - Advances in Radio Science
SN - 1684-9965
ER -