Details
| Originalsprache | Englisch |
|---|---|
| Titel des Sammelwerks | 23rd International Conference on Electrical Machines and Systems, ICEMS 2020 |
| Herausgeber (Verlag) | Institute of Electrical and Electronics Engineers Inc. |
| Seiten | 804-809 |
| Seitenumfang | 6 |
| ISBN (elektronisch) | 9784886864192 |
| ISBN (Print) | 978-1-7281-8930-7 |
| Publikationsstatus | Veröffentlicht - 2020 |
| Veranstaltung | 23rd International Conference on Electrical Machines and Systems, ICEMS 2020 - Hamamatsu, Japan Dauer: 24 Nov. 2020 → 27 Nov. 2020 |
Abstract
Temperature-Sensitive Electrical Parameters (TSEPs) are broadly discussed for on-line determination of the junction temperature of semiconductors and as key parameters for remaining lifetime estimation and degradation detection. Among the most prominent classes are forward voltage and switching times. Beside their dependency on load current and dc-link voltage, TSEPs used with large power modules in industry applications are affected by parasitic effects like gate drive voltage instability or temperature variations of added internal gate resistors. After calibrating TSEPs on the laboratory scale, the mapping between TSEP and temperature often fails when the inverter is operated in regular PWM mode. This paper focuses on parasitic effects that potentially cause deviations between TSEP calibration on the laboratory scale and regular operation of the inverter with focus on larger power modules. Multiple TSEPs are combined, aiming at an improved transferability of TSEPs between different modes of operation and robustness towards parasitics.
ASJC Scopus Sachgebiete
- Energie (insg.)
- Energieanlagenbau und Kraftwerkstechnik
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
- Ingenieurwesen (insg.)
- Maschinenbau
- Ingenieurwesen (insg.)
- Sicherheit, Risiko, Zuverlässigkeit und Qualität
- Mathematik (insg.)
- Steuerung und Optimierung
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23rd International Conference on Electrical Machines and Systems, ICEMS 2020. Institute of Electrical and Electronics Engineers Inc., 2020. S. 804-809 9291091.
Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review
}
TY - GEN
T1 - Impact of Parasitics in Power Modules and Gate Drivers on TSEP-based Temperature Estimations
AU - Herwig, Daniel
AU - Brockhage, Torben
AU - Mertens, Axel
N1 - Funding Information: This work was funded by the German Federal Ministry of Education and Research under the funding code 16EMO0325. The authors are responsible for the content of this publication.
PY - 2020
Y1 - 2020
N2 - Temperature-Sensitive Electrical Parameters (TSEPs) are broadly discussed for on-line determination of the junction temperature of semiconductors and as key parameters for remaining lifetime estimation and degradation detection. Among the most prominent classes are forward voltage and switching times. Beside their dependency on load current and dc-link voltage, TSEPs used with large power modules in industry applications are affected by parasitic effects like gate drive voltage instability or temperature variations of added internal gate resistors. After calibrating TSEPs on the laboratory scale, the mapping between TSEP and temperature often fails when the inverter is operated in regular PWM mode. This paper focuses on parasitic effects that potentially cause deviations between TSEP calibration on the laboratory scale and regular operation of the inverter with focus on larger power modules. Multiple TSEPs are combined, aiming at an improved transferability of TSEPs between different modes of operation and robustness towards parasitics.
AB - Temperature-Sensitive Electrical Parameters (TSEPs) are broadly discussed for on-line determination of the junction temperature of semiconductors and as key parameters for remaining lifetime estimation and degradation detection. Among the most prominent classes are forward voltage and switching times. Beside their dependency on load current and dc-link voltage, TSEPs used with large power modules in industry applications are affected by parasitic effects like gate drive voltage instability or temperature variations of added internal gate resistors. After calibrating TSEPs on the laboratory scale, the mapping between TSEP and temperature often fails when the inverter is operated in regular PWM mode. This paper focuses on parasitic effects that potentially cause deviations between TSEP calibration on the laboratory scale and regular operation of the inverter with focus on larger power modules. Multiple TSEPs are combined, aiming at an improved transferability of TSEPs between different modes of operation and robustness towards parasitics.
KW - Junction Temperature
KW - Measurement
KW - Mod-eling
KW - TSEP
UR - http://www.scopus.com/inward/record.url?scp=85099288902&partnerID=8YFLogxK
U2 - 10.23919/ICEMS50442.2020.9291091
DO - 10.23919/ICEMS50442.2020.9291091
M3 - Conference contribution
AN - SCOPUS:85099288902
SN - 978-1-7281-8930-7
SP - 804
EP - 809
BT - 23rd International Conference on Electrical Machines and Systems, ICEMS 2020
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 23rd International Conference on Electrical Machines and Systems, ICEMS 2020
Y2 - 24 November 2020 through 27 November 2020
ER -