Details
| Originalsprache | Englisch |
|---|---|
| Seiten (von - bis) | III/3112-III/3115 |
| Fachzeitschrift | Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP) |
| Jahrgang | 3 |
| Publikationsstatus | Veröffentlicht - 2002 |
| Veranstaltung | 2002 IEEE International Conference on Acoustic, Speech, and Signal Processing - Orlando, FL, USA / Vereinigte Staaten Dauer: 13 Mai 2002 → 17 Mai 2002 |
Abstract
The presented HiPAR-DSP is a highly parallel DSP core for system on a chip video- and image processing applications. The architecture is based on an array of up to 16 parallel data paths steered by a single RISC controller in SIMD style. Each data path consists of three VLIW controlled arithmetical units: a 16 bit MAC and 32 ALU and shift & round units. A divided memory concept serves local caches for each data path as well as a special shared matrix memory which enables concurrent access from all data paths in every clock cycle. External connection can be provided via a modular DMA controller which enables an easy interfacing to other on chip modules. The HiPAR-DSP core has been manufactured in the most powerful version with 16 data paths in second Quarter 2001 and delivers with a maximum clock frequency of 100 MHz 4.8 GOPS peak and about 3 GOPS sustained performance. In addition to the core architecture the paper will also present the software development system for the HiPAR-DSP including C/C++ compiler, assembler, simulator and a PCI board with onboard video I/O interfaces.
ASJC Scopus Sachgebiete
- Informatik (insg.)
- Software
- Informatik (insg.)
- Signalverarbeitung
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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in: Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP), Jahrgang 3, 2002, S. III/3112-III/3115.
Publikation: Beitrag in Fachzeitschrift › Konferenzaufsatz in Fachzeitschrift › Forschung › Peer-Review
}
TY - JOUR
T1 - HiPAR-DSP 16, scalable highly parallel DSP core for system on a chip video- and image processing applications
AU - Kloos, H.
AU - Wittenburg, J. P.
AU - Hinrichs, W.
AU - Lieske, H.
AU - Friebe, L.
AU - Klar, C.
AU - Pirsch, P.
PY - 2002
Y1 - 2002
N2 - The presented HiPAR-DSP is a highly parallel DSP core for system on a chip video- and image processing applications. The architecture is based on an array of up to 16 parallel data paths steered by a single RISC controller in SIMD style. Each data path consists of three VLIW controlled arithmetical units: a 16 bit MAC and 32 ALU and shift & round units. A divided memory concept serves local caches for each data path as well as a special shared matrix memory which enables concurrent access from all data paths in every clock cycle. External connection can be provided via a modular DMA controller which enables an easy interfacing to other on chip modules. The HiPAR-DSP core has been manufactured in the most powerful version with 16 data paths in second Quarter 2001 and delivers with a maximum clock frequency of 100 MHz 4.8 GOPS peak and about 3 GOPS sustained performance. In addition to the core architecture the paper will also present the software development system for the HiPAR-DSP including C/C++ compiler, assembler, simulator and a PCI board with onboard video I/O interfaces.
AB - The presented HiPAR-DSP is a highly parallel DSP core for system on a chip video- and image processing applications. The architecture is based on an array of up to 16 parallel data paths steered by a single RISC controller in SIMD style. Each data path consists of three VLIW controlled arithmetical units: a 16 bit MAC and 32 ALU and shift & round units. A divided memory concept serves local caches for each data path as well as a special shared matrix memory which enables concurrent access from all data paths in every clock cycle. External connection can be provided via a modular DMA controller which enables an easy interfacing to other on chip modules. The HiPAR-DSP core has been manufactured in the most powerful version with 16 data paths in second Quarter 2001 and delivers with a maximum clock frequency of 100 MHz 4.8 GOPS peak and about 3 GOPS sustained performance. In addition to the core architecture the paper will also present the software development system for the HiPAR-DSP including C/C++ compiler, assembler, simulator and a PCI board with onboard video I/O interfaces.
UR - http://www.scopus.com/inward/record.url?scp=11244301376&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:11244301376
VL - 3
SP - III/3112-III/3115
JO - Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP)
JF - Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP)
SN - 1520-6149
T2 - 2002 IEEE International Conference on Acoustic, Speech, and Signal Processing
Y2 - 13 May 2002 through 17 May 2002
ER -