HiPAR-DSP - a scalable family of high performance DSP-cores

Publikation: Beitrag in Fachzeitschrift › Konferenzaufsatz in Fachzeitschrift › Forschung › Peer-Review

Autoren

  • Jens Peter Wittenburg
  • Willm Hinrichs
  • Hanno Lieske
  • Helge Kloos
  • Lars Friebe
  • Peter Pirsch

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Details

OriginalspracheEnglisch
Seiten (von - bis)92-96
Seitenumfang5
FachzeitschriftProceedings of the Annual IEEE International ASIC Conference and Exhibit
PublikationsstatusVeröffentlicht - 2000
Veranstaltung13th Annual IEEE International ASIC/SOC Conference - Arlington, VA, USA
Dauer: 13 Sept. 2000 → 16 Sept. 2000

Abstract

With the HiPAR-DSP family we present a scalable series of high performance fixed point DSPs. The HiPAR-DSP family features up to 16 SIMD controlled datapaths, where each datapath consists of a VLIW controlled set of arithmetic units (16 bit Multiply & Accumulate, 32 bit ALU and 32 bit Shift & Round). A shared on-chip memory with specially adapted parallel access is used for communication between the datapaths. The number of datapaths can easily be scaled to adapt the architecture to requirements in terms of processing power and silicon area. A flexible DMA control unit allows easy interfacing for systems on a chip. The maximum configuration of the presented DSP family can sustain a processing power of more than 3 GOPS for actual applications.

ASJC Scopus Sachgebiete

Zitieren

HiPAR-DSP - a scalable family of high performance DSP-cores. / Wittenburg, Jens Peter; Hinrichs, Willm; Lieske, Hanno et al.
in: Proceedings of the Annual IEEE International ASIC Conference and Exhibit, 2000, S. 92-96.

Publikation: Beitrag in Fachzeitschrift › Konferenzaufsatz in Fachzeitschrift › Forschung › Peer-Review

Wittenburg, JP, Hinrichs, W, Lieske, H, Kloos, H, Friebe, L & Pirsch, P 2000, 'HiPAR-DSP - a scalable family of high performance DSP-cores', Proceedings of the Annual IEEE International ASIC Conference and Exhibit, S. 92-96.
Wittenburg, J. P., Hinrichs, W., Lieske, H., Kloos, H., Friebe, L., & Pirsch, P. (2000). HiPAR-DSP - a scalable family of high performance DSP-cores. Proceedings of the Annual IEEE International ASIC Conference and Exhibit, 92-96.
Wittenburg JP, Hinrichs W, Lieske H, Kloos H, Friebe L, Pirsch P. HiPAR-DSP - a scalable family of high performance DSP-cores. Proceedings of the Annual IEEE International ASIC Conference and Exhibit. 2000;92-96.
Wittenburg, Jens Peter ; Hinrichs, Willm ; Lieske, Hanno et al. / HiPAR-DSP - a scalable family of high performance DSP-cores. in: Proceedings of the Annual IEEE International ASIC Conference and Exhibit. 2000 ; S. 92-96.
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AU - Lieske, Hanno

AU - Kloos, Helge

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AU - Pirsch, Peter

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