Details
| Originalsprache | Englisch |
|---|---|
| Titel des Sammelwerks | 1997 3rd International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 1997 |
| Herausgeber/-innen | Wanlei Zhou, Andrzej Goscinski, Michael Hobbs |
| Herausgeber (Verlag) | Institute of Electrical and Electronics Engineers Inc. |
| Seiten | 155-162 |
| Seitenumfang | 8 |
| ISBN (elektronisch) | 0780342291, 9780780342293 |
| Publikationsstatus | Veröffentlicht - 1997 |
| Veranstaltung | 3rd International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 1997 - Melbourne, Australien Dauer: 10 Dez. 1997 → 12 Dez. 1997 |
Publikationsreihe
| Name | 1997 3rd International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 1997 |
|---|
Abstract
Derived from a thorough analysis of a wide class of image processing algorithms' properties, a parallel RISC architecture has been developed. The architecture gains performance from data level parallelism as well as from instruction level parallelism. From the beginning of the concept phase, high-level programming capabilities have been one of the major design goals. Thus, there has been a steady interaction between the design of the software development toolkit-optimizing assembler and C++ compiler-and the architecture itself. The RISC-typical register files are one of the most critical elements as well concerning die size and clock frequency as the assembler's ability in VLIW scheduling. Running at 100 MHz (200 mm 2 , 0.35 μm CMOS) the processor reaches a sustained performance of more than 2 GOPS for a wide range of image processing algorithms.
ASJC Scopus Sachgebiete
- Informatik (insg.)
- Computernetzwerke und -kommunikation
- Informatik (insg.)
- Hardware und Architektur
- Informatik (insg.)
- Signalverarbeitung
Zitieren
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- BibTex
- RIS
1997 3rd International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 1997. Hrsg. / Wanlei Zhou; Andrzej Goscinski; Michael Hobbs. Institute of Electrical and Electronics Engineers Inc., 1997. S. 155-162 651487 (1997 3rd International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 1997).
Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review
}
TY - GEN
T1 - HiPAR-DSP
T2 - 3rd International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 1997
AU - Wittenburg, J. P.
AU - Ohmacht, M.
AU - Kneip, J.
AU - Hinrichs, W.
AU - Pirsch, P.
PY - 1997
Y1 - 1997
N2 - Derived from a thorough analysis of a wide class of image processing algorithms' properties, a parallel RISC architecture has been developed. The architecture gains performance from data level parallelism as well as from instruction level parallelism. From the beginning of the concept phase, high-level programming capabilities have been one of the major design goals. Thus, there has been a steady interaction between the design of the software development toolkit-optimizing assembler and C++ compiler-and the architecture itself. The RISC-typical register files are one of the most critical elements as well concerning die size and clock frequency as the assembler's ability in VLIW scheduling. Running at 100 MHz (200 mm 2 , 0.35 μm CMOS) the processor reaches a sustained performance of more than 2 GOPS for a wide range of image processing algorithms.
AB - Derived from a thorough analysis of a wide class of image processing algorithms' properties, a parallel RISC architecture has been developed. The architecture gains performance from data level parallelism as well as from instruction level parallelism. From the beginning of the concept phase, high-level programming capabilities have been one of the major design goals. Thus, there has been a steady interaction between the design of the software development toolkit-optimizing assembler and C++ compiler-and the architecture itself. The RISC-typical register files are one of the most critical elements as well concerning die size and clock frequency as the assembler's ability in VLIW scheduling. Running at 100 MHz (200 mm 2 , 0.35 μm CMOS) the processor reaches a sustained performance of more than 2 GOPS for a wide range of image processing algorithms.
UR - http://www.scopus.com/inward/record.url?scp=33645150188&partnerID=8YFLogxK
U2 - 10.1109/ICAPP.1997.651487
DO - 10.1109/ICAPP.1997.651487
M3 - Conference contribution
AN - SCOPUS:33645150188
T3 - 1997 3rd International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 1997
SP - 155
EP - 162
BT - 1997 3rd International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 1997
A2 - Zhou, Wanlei
A2 - Goscinski, Andrzej
A2 - Hobbs, Michael
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 10 December 1997 through 12 December 1997
ER -