High Performance and Low Power Architectures: GPU vs. FPGA for Fast Factorized Backprojection

Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review

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OriginalspracheEnglisch
Titel des Sammelwerks2017 Fifth International Symposium on Computing and Networking
Herausgeber (Verlag)IEEE Computer Society
Seiten351-357
Seitenumfang7
ISBN (elektronisch)9781538620878
ISBN (Print)978-1-5386-2088-5
PublikationsstatusVeröffentlicht - 2 Juli 2017
Veranstaltung5th International Symposium on Computing and Networking, CANDAR 2017 - Aomori, Japan
Dauer: 19 Nov. 2017 → 22 Nov. 2017

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High Performance and Low Power Architectures: GPU vs. FPGA for Fast Factorized Backprojection. / Wielage, M.; Cholewa, F.; Fahnemann, C. et al.
2017 Fifth International Symposium on Computing and Networking. IEEE Computer Society, 2017. S. 351-357.

Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review

Wielage, M, Cholewa, F, Fahnemann, C, Pirsch, P & Blume, H 2017, High Performance and Low Power Architectures: GPU vs. FPGA for Fast Factorized Backprojection. in 2017 Fifth International Symposium on Computing and Networking. IEEE Computer Society, S. 351-357, 5th International Symposium on Computing and Networking, CANDAR 2017, Aomori, Japan, 19 Nov. 2017. https://doi.org/10.1109/CANDAR.2017.101
Wielage, M., Cholewa, F., Fahnemann, C., Pirsch, P., & Blume, H. (2017). High Performance and Low Power Architectures: GPU vs. FPGA for Fast Factorized Backprojection. In 2017 Fifth International Symposium on Computing and Networking (S. 351-357). IEEE Computer Society. https://doi.org/10.1109/CANDAR.2017.101
Wielage M, Cholewa F, Fahnemann C, Pirsch P, Blume H. High Performance and Low Power Architectures: GPU vs. FPGA for Fast Factorized Backprojection. in 2017 Fifth International Symposium on Computing and Networking. IEEE Computer Society. 2017. S. 351-357 doi: 10.1109/CANDAR.2017.101
Wielage, M. ; Cholewa, F. ; Fahnemann, C. et al. / High Performance and Low Power Architectures : GPU vs. FPGA for Fast Factorized Backprojection. 2017 Fifth International Symposium on Computing and Networking. IEEE Computer Society, 2017. S. 351-357
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@inproceedings{b4e78516badb41089996e3ecc46943da,
title = "High Performance and Low Power Architectures: GPU vs. FPGA for Fast Factorized Backprojection",
keywords = "Fast Factorized Backprojection, FPGA, GPU, Power-Efficiency, Radar, SAR",
author = "M. Wielage and F. Cholewa and C. Fahnemann and P. Pirsch and H. Blume",
year = "2017",
month = jul,
day = "2",
doi = "10.1109/CANDAR.2017.101",
language = "English",
isbn = "978-1-5386-2088-5",
pages = "351--357",
booktitle = "2017 Fifth International Symposium on Computing and Networking",
publisher = "IEEE Computer Society",
address = "United States",
note = "5th International Symposium on Computing and Networking, CANDAR 2017 ; Conference date: 19-11-2017 Through 22-11-2017",

}

Download

TY - GEN

T1 - High Performance and Low Power Architectures

T2 - 5th International Symposium on Computing and Networking, CANDAR 2017

AU - Wielage, M.

AU - Cholewa, F.

AU - Fahnemann, C.

AU - Pirsch, P.

AU - Blume, H.

PY - 2017/7/2

Y1 - 2017/7/2

KW - Fast Factorized Backprojection

KW - FPGA

KW - GPU

KW - Power-Efficiency

KW - Radar

KW - SAR

U2 - 10.1109/CANDAR.2017.101

DO - 10.1109/CANDAR.2017.101

M3 - Conference contribution

AN - SCOPUS:85050293878

SN - 978-1-5386-2088-5

SP - 351

EP - 357

BT - 2017 Fifth International Symposium on Computing and Networking

PB - IEEE Computer Society

Y2 - 19 November 2017 through 22 November 2017

ER -

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