TY - JOUR

T1 - HiBRID-SoC

T2 - A multi-core SoC architecture for multimedia signal processing

AU - Stolberg, Hans Joachim

AU - Bereković, Mladen

AU - Moch, Sören

AU - Friebe, Lars

AU - Kulaczewski, Mark B.

AU - Flügel, Sebastian

AU - Klußmann, Heiko

AU - Dehnhardt, Andreas

AU - Pirsch, Peter

N1 - Funding Information: This work was funded by the Fraunhofer Gesellschaft under contract T/F31D/1A232/P1307. The authors would like to thank X. Mao for design contributions and Micronas GmbH for tape-out support.

PY - 2005/8/1

Y1 - 2005/8/1

N2 - The HiBRID-SoC multi-core system-on-chip architecture targets a wide range of multimedia applications with particularly high processing demands, including general signal processing applications, video de-/encoding, image processing, or a combination of these tasks. For this purpose, the HiBRID-SoC integrates three fully programmable processors cores and various interfaces onto a single chip, all tied to a 64-Bit AMBA AHB bus. The processor cores are individually optimized to the particular computational characteristics of different application fields, complementing each other to deliver high performance levels with high flexibility at reduced system cost. The HiBRID-SoC is fabricated in a 0.18 μm 6LM standard-cell CMOS technology, occupies about 81 mm2, and operates at 145 MHz. An MPEG-4 Advanced Simple Profile decoder in full D1 resolution requires about 120 MHz for real-time operation on the HiBRID-SoC, utilizing only two of the three cores. Together with the third core, a custom region-of-interest (ROI) based surveillance application can be built.

AB - The HiBRID-SoC multi-core system-on-chip architecture targets a wide range of multimedia applications with particularly high processing demands, including general signal processing applications, video de-/encoding, image processing, or a combination of these tasks. For this purpose, the HiBRID-SoC integrates three fully programmable processors cores and various interfaces onto a single chip, all tied to a 64-Bit AMBA AHB bus. The processor cores are individually optimized to the particular computational characteristics of different application fields, complementing each other to deliver high performance levels with high flexibility at reduced system cost. The HiBRID-SoC is fabricated in a 0.18 μm 6LM standard-cell CMOS technology, occupies about 81 mm2, and operates at 145 MHz. An MPEG-4 Advanced Simple Profile decoder in full D1 resolution requires about 120 MHz for real-time operation on the HiBRID-SoC, utilizing only two of the three cores. Together with the third core, a custom region-of-interest (ROI) based surveillance application can be built.

KW - MPEG-4

KW - Multi-core

KW - Multimedia

KW - Surveillance

KW - System-on-chip

KW - VLSI

UR - http://www.scopus.com/inward/record.url?scp=21544448122&partnerID=8YFLogxK

U2 - 10.1007/s11265-005-6247-1

DO - 10.1007/s11265-005-6247-1

M3 - Article

AN - SCOPUS:21544448122

VL - 41

SP - 9

EP - 20

JO - Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

JF - Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology

SN - 1387-5485

IS - 1

ER -