Details
| Originalsprache | Englisch |
|---|---|
| Seiten (von - bis) | 417-424 |
| Seitenumfang | 8 |
| Fachzeitschrift | Proceedings of SPIE - The International Society for Optical Engineering |
| Jahrgang | 1977 |
| Publikationsstatus | Veröffentlicht - 29 Okt. 1993 |
| Veranstaltung | Video Communications and PACS for Medical Applications 1993 - Berlin, Deutschland Dauer: 4 Apr. 1993 → 9 Apr. 1993 |
Abstract
A multiprocessor architecture for compact realizations of video coding applications is presented. The actual standards for video coding e.g. H.261 and MPEG are based on a hybrid coding scheme, which allows parallelization at both data level and task level. The parallelization at data level is performed by distribution of image data among the processors. Each processor works on locally stored image segments. The parallelization at task level is realized inside the processors by functional modules which are adapted to classes of algorithms. The functionality of the modules and the number of their data paths is determined by applying efficiency calculations resulting in a module for motion estimation and a blocklevel coprocessor for transform and quantization. The controlling and synchronization is accomplished by a programmable module. A hierarchical controlling concept reduces the on-chip control overhead. A chip size of 70 mm2 is estimated for one processor, when using 0.6 μm CMOS technology. With an operating frequency of 65 MHz one chip will perform the computations for a full CIF H.261 codec with 30 Hz framerate and motion estimation based on +/-15 pel full search blockmatching algorithm.
ASJC Scopus Sachgebiete
- Werkstoffwissenschaften (insg.)
- Elektronische, optische und magnetische Materialien
- Physik und Astronomie (insg.)
- Physik der kondensierten Materie
- Informatik (insg.)
- Angewandte Informatik
- Mathematik (insg.)
- Angewandte Mathematik
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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in: Proceedings of SPIE - The International Society for Optical Engineering, Jahrgang 1977, 29.10.1993, S. 417-424.
Publikation: Beitrag in Fachzeitschrift › Konferenzaufsatz in Fachzeitschrift › Forschung › Peer-Review
}
TY - JOUR
T1 - Heterogeneous multiprocessor architecure for video coding applications
AU - Hoffer, Richard
AU - Gehrke, Winfried
AU - Pirsch, Peter
N1 - Funding Information: This work is supported by the Corporate Research and Development Siemens AG, Munich.
PY - 1993/10/29
Y1 - 1993/10/29
N2 - A multiprocessor architecture for compact realizations of video coding applications is presented. The actual standards for video coding e.g. H.261 and MPEG are based on a hybrid coding scheme, which allows parallelization at both data level and task level. The parallelization at data level is performed by distribution of image data among the processors. Each processor works on locally stored image segments. The parallelization at task level is realized inside the processors by functional modules which are adapted to classes of algorithms. The functionality of the modules and the number of their data paths is determined by applying efficiency calculations resulting in a module for motion estimation and a blocklevel coprocessor for transform and quantization. The controlling and synchronization is accomplished by a programmable module. A hierarchical controlling concept reduces the on-chip control overhead. A chip size of 70 mm2 is estimated for one processor, when using 0.6 μm CMOS technology. With an operating frequency of 65 MHz one chip will perform the computations for a full CIF H.261 codec with 30 Hz framerate and motion estimation based on +/-15 pel full search blockmatching algorithm.
AB - A multiprocessor architecture for compact realizations of video coding applications is presented. The actual standards for video coding e.g. H.261 and MPEG are based on a hybrid coding scheme, which allows parallelization at both data level and task level. The parallelization at data level is performed by distribution of image data among the processors. Each processor works on locally stored image segments. The parallelization at task level is realized inside the processors by functional modules which are adapted to classes of algorithms. The functionality of the modules and the number of their data paths is determined by applying efficiency calculations resulting in a module for motion estimation and a blocklevel coprocessor for transform and quantization. The controlling and synchronization is accomplished by a programmable module. A hierarchical controlling concept reduces the on-chip control overhead. A chip size of 70 mm2 is estimated for one processor, when using 0.6 μm CMOS technology. With an operating frequency of 65 MHz one chip will perform the computations for a full CIF H.261 codec with 30 Hz framerate and motion estimation based on +/-15 pel full search blockmatching algorithm.
UR - http://www.scopus.com/inward/record.url?scp=0346050893&partnerID=8YFLogxK
U2 - 10.1117/12.160486
DO - 10.1117/12.160486
M3 - Conference article
AN - SCOPUS:0346050893
VL - 1977
SP - 417
EP - 424
JO - Proceedings of SPIE - The International Society for Optical Engineering
JF - Proceedings of SPIE - The International Society for Optical Engineering
SN - 0277-786X
T2 - Video Communications and PACS for Medical Applications 1993
Y2 - 4 April 1993 through 9 April 1993
ER -