Details
| Originalsprache | Englisch |
|---|---|
| Titel des Sammelwerks | 2024 9th International Conference on Frontiers of Signal Processing, ICFSP 2024 |
| Herausgeber (Verlag) | Institute of Electrical and Electronics Engineers Inc. |
| Seiten | 174-178 |
| Seitenumfang | 5 |
| ISBN (elektronisch) | 9798350353235 |
| ISBN (Print) | 979-8-3503-5324-2 |
| Publikationsstatus | Veröffentlicht - 12 Sept. 2024 |
| Veranstaltung | 9th International Conference on Frontiers of Signal Processing, ICFSP 2024 - Paris, Frankreich Dauer: 12 Sept. 2024 → 14 Sept. 2024 |
Abstract
Sparse Bayesian algorithms have attracted a lot of attention in various application areas for solving sparse recovery problems. One of these is the direction-of-arrival estimation in automotive radar due to the super-resolution capability. However, the computational complexity makes real-time capable implementations on state-of-the-art embedded platforms difficult. To tackle this challenge, we combine three techniques in this work resulting in a hardware-friendly sparse variational Bayesian algorithm that can handle high accuracy and throughputs with reasonable hardware costs. Firstly, we apply intra-iteration speed-up via angular decoupling of the calculations. Secondly, a highly efficient convergence acceleration technique based on exponential weighting is developed, which features minimal additional memory demand. Lastly, we derive a division-free algorithm by interlacing the algorithm with Newton's method. This reduces the demands on the utilized hardware platform and enables the implementation of the algorithm on embedded, power- and cost-optimized FPGAs and ASICs. The proposed algorithm is implemented on a novel application specific AI processor featuring a massive parallel vertical vector architecture as well as on a PC for benchmarking purposes. The results are compared to state-of-the-art algorithms.
ASJC Scopus Sachgebiete
- Informatik (insg.)
- Artificial intelligence
- Informatik (insg.)
- Maschinelles Sehen und Mustererkennung
- Informatik (insg.)
- Signalverarbeitung
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2024 9th International Conference on Frontiers of Signal Processing, ICFSP 2024. Institute of Electrical and Electronics Engineers Inc., 2024. S. 174-178.
Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review
}
TY - GEN
T1 - Hardware-Friendly Variational Bayesian Method for DoA Estimation in Automotive MIMO Radar
AU - Jauch, Alisa
AU - Meinl, Frank
AU - Blume, Holger
N1 - Publisher Copyright: © 2024 IEEE.
PY - 2024/9/12
Y1 - 2024/9/12
N2 - Sparse Bayesian algorithms have attracted a lot of attention in various application areas for solving sparse recovery problems. One of these is the direction-of-arrival estimation in automotive radar due to the super-resolution capability. However, the computational complexity makes real-time capable implementations on state-of-the-art embedded platforms difficult. To tackle this challenge, we combine three techniques in this work resulting in a hardware-friendly sparse variational Bayesian algorithm that can handle high accuracy and throughputs with reasonable hardware costs. Firstly, we apply intra-iteration speed-up via angular decoupling of the calculations. Secondly, a highly efficient convergence acceleration technique based on exponential weighting is developed, which features minimal additional memory demand. Lastly, we derive a division-free algorithm by interlacing the algorithm with Newton's method. This reduces the demands on the utilized hardware platform and enables the implementation of the algorithm on embedded, power- and cost-optimized FPGAs and ASICs. The proposed algorithm is implemented on a novel application specific AI processor featuring a massive parallel vertical vector architecture as well as on a PC for benchmarking purposes. The results are compared to state-of-the-art algorithms.
AB - Sparse Bayesian algorithms have attracted a lot of attention in various application areas for solving sparse recovery problems. One of these is the direction-of-arrival estimation in automotive radar due to the super-resolution capability. However, the computational complexity makes real-time capable implementations on state-of-the-art embedded platforms difficult. To tackle this challenge, we combine three techniques in this work resulting in a hardware-friendly sparse variational Bayesian algorithm that can handle high accuracy and throughputs with reasonable hardware costs. Firstly, we apply intra-iteration speed-up via angular decoupling of the calculations. Secondly, a highly efficient convergence acceleration technique based on exponential weighting is developed, which features minimal additional memory demand. Lastly, we derive a division-free algorithm by interlacing the algorithm with Newton's method. This reduces the demands on the utilized hardware platform and enables the implementation of the algorithm on embedded, power- and cost-optimized FPGAs and ASICs. The proposed algorithm is implemented on a novel application specific AI processor featuring a massive parallel vertical vector architecture as well as on a PC for benchmarking purposes. The results are compared to state-of-the-art algorithms.
KW - application-specific processor
KW - automotive MIMO radar
KW - Bayes methods
KW - Direction-of-arrival estimation
UR - http://www.scopus.com/inward/record.url?scp=85215705420&partnerID=8YFLogxK
U2 - 10.1109/ICFSP62546.2024.10785290
DO - 10.1109/ICFSP62546.2024.10785290
M3 - Conference contribution
AN - SCOPUS:85215705420
SN - 979-8-3503-5324-2
SP - 174
EP - 178
BT - 2024 9th International Conference on Frontiers of Signal Processing, ICFSP 2024
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 9th International Conference on Frontiers of Signal Processing, ICFSP 2024
Y2 - 12 September 2024 through 14 September 2024
ER -