Hardware-assisted power estimation for design-stage processors using FPGA emulation

Sebastian Hesselbarth; Tim Baumgart; Holger Blume

doi:10.1109/PATMOS.2014.6951877

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Originalsprache	Englisch
Titel des Sammelwerks	2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)
Herausgeber (Verlag)	IEEE Computer Society
ISBN (elektronisch)	9781479954124
Publikationsstatus	Veröffentlicht - 13 Nov. 2014
Veranstaltung	2014 International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2014 - Palma de Mallorca, Spanien Dauer: 29 Sept. 2014 → 1 Okt. 2014 Konferenznummer: 24

ASJC Scopus Sachgebiete

Energie (insg.)
Energieanlagenbau und Kraftwerkstechnik
Mathematik (insg.)
Modellierung und Simulation

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Hardware-assisted power estimation for design-stage processors using FPGA emulation. / Hesselbarth, Sebastian; Baumgart, Tim; Blume, Holger.
2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). IEEE Computer Society, 2014.

Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review

Hesselbarth, S, Baumgart, T & Blume, H 2014, Hardware-assisted power estimation for design-stage processors using FPGA emulation. in 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). IEEE Computer Society, 2014 International Workshop on Power and Timing Modeling, Optimization and Simulation, PATMOS 2014, Palma de Mallorca, Spanien, 29 Sept. 2014. https://doi.org/10.1109/PATMOS.2014.6951877

Hesselbarth, S., Baumgart, T., & Blume, H. (2014). Hardware-assisted power estimation for design-stage processors using FPGA emulation. In 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) IEEE Computer Society. https://doi.org/10.1109/PATMOS.2014.6951877

Hesselbarth S, Baumgart T, Blume H. Hardware-assisted power estimation for design-stage processors using FPGA emulation. in 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). IEEE Computer Society. 2014 doi: 10.1109/PATMOS.2014.6951877

Hesselbarth, Sebastian ; Baumgart, Tim ; Blume, Holger. / Hardware-assisted power estimation for design-stage processors using FPGA emulation. 2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS). IEEE Computer Society, 2014.

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author = "Sebastian Hesselbarth and Tim Baumgart and Holger Blume",

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Research@Leibniz University

Hardware-assisted power estimation for design-stage processors using FPGA emulation

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