Hardware realization of a Java Virtual Machine for high performance multimedia applications

Publikation: KonferenzbeitragPaperForschungPeer-Review

Autoren

  • Mladen Berekovic
  • Helge Kloos
  • Peter Pirsch
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Details

OriginalspracheEnglisch
Seiten479-488
Seitenumfang10
PublikationsstatusVeröffentlicht - 1997
Veranstaltung1997 IEEE Workshop on Signal Processing Systems, SiPS 97: Design and Implementation - Leicester, UK
Dauer: 3 Nov. 19975 Nov. 1997

Konferenz

Konferenz1997 IEEE Workshop on Signal Processing Systems, SiPS 97: Design and Implementation
OrtLeicester, UK
Zeitraum3 Nov. 19975 Nov. 1997

Abstract

This paper describes a new architecture for content-based, interactive multimedia applications. A hardware implementation of a Java Virtual Machine (JVM) is proposed, which allows for direct execution of Java bytecode. In a single clock cycle, up to 3 bytecode instructions can be decoded and executed in parallel using a RISC pipeline. A splitable 64-bit ALU implementation addresses demanding processing requirements of typical multimedia signal processing schemes. The proposed architecture supports parallel execution of multiple Java threads. An implementation of basic building blocks of the processor with a standard-cell library provides an estimate of 150 MHz clock-speed for a 0.35 μm 3 metal layer CMOS process. With a size of less than 10 mm2 needed for the core logic, it is possible to integrate multiple JVMs together with larger cache memories on a single chip.

ASJC Scopus Sachgebiete

Zitieren

Hardware realization of a Java Virtual Machine for high performance multimedia applications. / Berekovic, Mladen; Kloos, Helge; Pirsch, Peter.
1997. 479-488 Beitrag in 1997 IEEE Workshop on Signal Processing Systems, SiPS 97: Design and Implementation, Leicester, UK.

Publikation: KonferenzbeitragPaperForschungPeer-Review

Berekovic, M, Kloos, H & Pirsch, P 1997, 'Hardware realization of a Java Virtual Machine for high performance multimedia applications', Beitrag in 1997 IEEE Workshop on Signal Processing Systems, SiPS 97: Design and Implementation, Leicester, UK, 3 Nov. 1997 - 5 Nov. 1997 S. 479-488.
Berekovic, M., Kloos, H., & Pirsch, P. (1997). Hardware realization of a Java Virtual Machine for high performance multimedia applications. 479-488. Beitrag in 1997 IEEE Workshop on Signal Processing Systems, SiPS 97: Design and Implementation, Leicester, UK.
Berekovic M, Kloos H, Pirsch P. Hardware realization of a Java Virtual Machine for high performance multimedia applications. 1997. Beitrag in 1997 IEEE Workshop on Signal Processing Systems, SiPS 97: Design and Implementation, Leicester, UK.
Berekovic, Mladen ; Kloos, Helge ; Pirsch, Peter. / Hardware realization of a Java Virtual Machine for high performance multimedia applications. Beitrag in 1997 IEEE Workshop on Signal Processing Systems, SiPS 97: Design and Implementation, Leicester, UK.10 S.
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