Details
| Originalsprache | Englisch |
|---|---|
| Titel des Sammelwerks | ESSCIRC 2016 |
| Untertitel | 42nd European Solid-State Circuits Conference |
| Seiten | 325-328 |
| Seitenumfang | 4 |
| ISBN (elektronisch) | 9781509029723 |
| Publikationsstatus | Veröffentlicht - 18 Okt. 2016 |
| Extern publiziert | Ja |
| Veranstaltung | 42nd European Solid-State Circuits Conference, ESSCIRC 2016 - Lausanne, Schweiz Dauer: 12 Sept. 2016 → 15 Sept. 2016 |
Publikationsreihe
| Name | European Solid-State Circuits Conference |
|---|---|
| Band | 2016-October |
| ISSN (Print) | 1930-8833 |
Abstract
In various fields, there is a growing need for electric motor drives and inductive power converters. To achieve better switching behavior and lower EME in inductive switching applications, very precise gate control of the power MOSFETs by the gate driver is required. The driver presented in this paper can operate at voltages up to 60V, and it is able to change the gate current in 10 / 15ns (rise / fall delay) within a range of 20mA to 500mA. Achieved by a class B buffer in the output stage, this enables multiple current changes in a 100ns switching transition. A dip in the output current, caused by parasitic capacitances, is reduced from 80% of the full scale current to 20% by a cascode configuration in the driver output stage. The gate voltage is clamped to 11.5V, with a precise clamping circuit to reduce RDS,on with the full gate current, but without stressing the gate oxide with any over voltage. By fully integrating this concept in 130nm HV-BiCMOS, a reduction in external components for limiting overshoot, stress and EME can be achieved.
ASJC Scopus Sachgebiete
- Informatik (insg.)
- Hardware und Architektur
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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ESSCIRC 2016: 42nd European Solid-State Circuits Conference. 2016. S. 325-328 7598308 (European Solid-State Circuits Conference; Band 2016-October).
Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review
}
TY - GEN
T1 - Gate driver with 10 / 15ns in-transition variable drive current and 60% reduced current dip
AU - Schindler, Alexis
AU - Koeppl, Benno
AU - Pottbaecker, Ansgar
AU - Zannoth, Markus
AU - Wicht, Bernhard
N1 - Publisher Copyright: © 2016 IEEE.
PY - 2016/10/18
Y1 - 2016/10/18
N2 - In various fields, there is a growing need for electric motor drives and inductive power converters. To achieve better switching behavior and lower EME in inductive switching applications, very precise gate control of the power MOSFETs by the gate driver is required. The driver presented in this paper can operate at voltages up to 60V, and it is able to change the gate current in 10 / 15ns (rise / fall delay) within a range of 20mA to 500mA. Achieved by a class B buffer in the output stage, this enables multiple current changes in a 100ns switching transition. A dip in the output current, caused by parasitic capacitances, is reduced from 80% of the full scale current to 20% by a cascode configuration in the driver output stage. The gate voltage is clamped to 11.5V, with a precise clamping circuit to reduce RDS,on with the full gate current, but without stressing the gate oxide with any over voltage. By fully integrating this concept in 130nm HV-BiCMOS, a reduction in external components for limiting overshoot, stress and EME can be achieved.
AB - In various fields, there is a growing need for electric motor drives and inductive power converters. To achieve better switching behavior and lower EME in inductive switching applications, very precise gate control of the power MOSFETs by the gate driver is required. The driver presented in this paper can operate at voltages up to 60V, and it is able to change the gate current in 10 / 15ns (rise / fall delay) within a range of 20mA to 500mA. Achieved by a class B buffer in the output stage, this enables multiple current changes in a 100ns switching transition. A dip in the output current, caused by parasitic capacitances, is reduced from 80% of the full scale current to 20% by a cascode configuration in the driver output stage. The gate voltage is clamped to 11.5V, with a precise clamping circuit to reduce RDS,on with the full gate current, but without stressing the gate oxide with any over voltage. By fully integrating this concept in 130nm HV-BiCMOS, a reduction in external components for limiting overshoot, stress and EME can be achieved.
UR - http://www.scopus.com/inward/record.url?scp=84994460761&partnerID=8YFLogxK
U2 - 10.1109/esscirc.2016.7598308
DO - 10.1109/esscirc.2016.7598308
M3 - Conference contribution
AN - SCOPUS:84994460761
T3 - European Solid-State Circuits Conference
SP - 325
EP - 328
BT - ESSCIRC 2016
T2 - 42nd European Solid-State Circuits Conference, ESSCIRC 2016
Y2 - 12 September 2016 through 15 September 2016
ER -