Details
| Originalsprache | Englisch |
|---|---|
| Seiten (von - bis) | 14-25 |
| Seitenumfang | 12 |
| Fachzeitschrift | Journal of Systems Architecture |
| Jahrgang | 77 |
| Publikationsstatus | Veröffentlicht - 24 Dez. 2016 |
ASJC Scopus Sachgebiete
- Informatik (insg.)
- Software
- Informatik (insg.)
- Hardware und Architektur
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FPGA emulation methodology for fast and accurate power estimation of embedded processors. / Hesselbarth, S.; Schewior, G.; Blume, H.
in: Journal of Systems Architecture, Jahrgang 77, 24.12.2016, S. 14-25.
in: Journal of Systems Architecture, Jahrgang 77, 24.12.2016, S. 14-25.
Publikation: Beitrag in Fachzeitschrift › Artikel › Forschung › Peer-Review
Hesselbarth, S, Schewior, G & Blume, H 2016, 'FPGA emulation methodology for fast and accurate power estimation of embedded processors', Journal of Systems Architecture, Jg. 77, S. 14-25. https://doi.org/10.1016/j.sysarc.2016.12.008
Hesselbarth, S., Schewior, G., & Blume, H. (2016). FPGA emulation methodology for fast and accurate power estimation of embedded processors. Journal of Systems Architecture, 77, 14-25. https://doi.org/10.1016/j.sysarc.2016.12.008
Hesselbarth S, Schewior G, Blume H. FPGA emulation methodology for fast and accurate power estimation of embedded processors. Journal of Systems Architecture. 2016 Dez 24;77:14-25. doi: 10.1016/j.sysarc.2016.12.008
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title = "FPGA emulation methodology for fast and accurate power estimation of embedded processors",
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T1 - FPGA emulation methodology for fast and accurate power estimation of embedded processors
AU - Hesselbarth, S.
AU - Schewior, G.
AU - Blume, H.
PY - 2016/12/24
Y1 - 2016/12/24
KW - Methodology
KW - Power emulation
KW - Power estimation
KW - Processors
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DO - 10.1016/j.sysarc.2016.12.008
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SP - 14
EP - 25
JO - Journal of Systems Architecture
JF - Journal of Systems Architecture
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