FLINT:: Layout-Oriented FPGA-Based Methodology for Fault Tolerant ASIC Design

Rochus Nowosielski; Lukas Gerlach; Stephan Bieband; Guillermo Paya-Vaya; Holger Blume

doi:10.7873/DATE.2015.0278

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Originalsprache	Englisch
Titel des Sammelwerks	Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition (DATE)
Herausgeber (Verlag)	IEEE Computer Society
Seiten	297-300
Seitenumfang	4
ISBN (elektronisch)	9783981537048
Publikationsstatus	Veröffentlicht - 22 Apr. 2015
Veranstaltung	2015 Design, Automation and Test in Europe Conference and Exhibition (DATE) - Grenoble, Frankreich Dauer: 9 März 2015 → 13 März 2015

ASJC Scopus Sachgebiete

Ingenieurwesen (insg.)
Allgemeiner Maschinenbau

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FLINT: Layout-Oriented FPGA-Based Methodology for Fault Tolerant ASIC Design. / Nowosielski, Rochus; Gerlach, Lukas; Bieband, Stephan et al.
Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition (DATE). IEEE Computer Society, 2015. S. 297-300.

Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review

Nowosielski, R, Gerlach, L, Bieband, S, Paya-Vaya, G & Blume, H 2015, FLINT: Layout-Oriented FPGA-Based Methodology for Fault Tolerant ASIC Design. in Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition (DATE). IEEE Computer Society, S. 297-300, 2015 Design, Automation and Test in Europe Conference and Exhibition (DATE), Grenoble, Frankreich, 9 März 2015. https://doi.org/10.7873/DATE.2015.0278

Nowosielski, R., Gerlach, L., Bieband, S., Paya-Vaya, G., & Blume, H. (2015). FLINT: Layout-Oriented FPGA-Based Methodology for Fault Tolerant ASIC Design. In Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition (DATE) (S. 297-300). IEEE Computer Society. https://doi.org/10.7873/DATE.2015.0278

Nowosielski R, Gerlach L, Bieband S, Paya-Vaya G, Blume H. FLINT: Layout-Oriented FPGA-Based Methodology for Fault Tolerant ASIC Design. in Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition (DATE). IEEE Computer Society. 2015. S. 297-300 doi: 10.7873/DATE.2015.0278

Nowosielski, Rochus ; Gerlach, Lukas ; Bieband, Stephan et al. / FLINT: Layout-Oriented FPGA-Based Methodology for Fault Tolerant ASIC Design. Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition (DATE). IEEE Computer Society, 2015. S. 297-300

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Research@Leibniz University

FLINT: Layout-Oriented FPGA-Based Methodology for Fault Tolerant ASIC Design

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