Details
| Originalsprache | Englisch |
|---|---|
| Titel des Sammelwerks | Proceedings |
| Untertitel | IEEE International Symposium on Circuits and Systems |
| Seiten | 1583-1586 |
| Seitenumfang | 4 |
| Publikationsstatus | Veröffentlicht - 1993 |
| Veranstaltung | 1993 IEEE International Symposium on Circuits and Systems - Chicago, IL, USA Dauer: 3 Mai 1993 → 6 Mai 1993 |
Publikationsreihe
| Name | Proceedings - IEEE International Symposium on Circuits and Systems |
|---|---|
| Band | 3 |
| ISSN (Print) | 0271-4310 |
Abstract
A fault-tolerant DCT-architecture based on distributed arithmetic has been developed. Fault-tolerance is achieved through a combination of distributed and residue arithmetic units. The implementation area of the presented architecture is about twice the size of a standard, non-fault-tolerant realization. Simulations on gate-level have shown, that about 75% of the logic area are protected against single static or dynamic stuck-at faults.
ASJC Scopus Sachgebiete
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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Proceedings : IEEE International Symposium on Circuits and Systems. 1993. S. 1583-1586 (Proceedings - IEEE International Symposium on Circuits and Systems; Band 3).
Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review
}
TY - GEN
T1 - Fault-tolerant DCT-architecture based on distributed arithmetic
AU - Gaedke, Klaus
AU - Franzen, Jens
AU - Pirsch, Peter
PY - 1993
Y1 - 1993
N2 - A fault-tolerant DCT-architecture based on distributed arithmetic has been developed. Fault-tolerance is achieved through a combination of distributed and residue arithmetic units. The implementation area of the presented architecture is about twice the size of a standard, non-fault-tolerant realization. Simulations on gate-level have shown, that about 75% of the logic area are protected against single static or dynamic stuck-at faults.
AB - A fault-tolerant DCT-architecture based on distributed arithmetic has been developed. Fault-tolerance is achieved through a combination of distributed and residue arithmetic units. The implementation area of the presented architecture is about twice the size of a standard, non-fault-tolerant realization. Simulations on gate-level have shown, that about 75% of the logic area are protected against single static or dynamic stuck-at faults.
UR - http://www.scopus.com/inward/record.url?scp=0027245243&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0027245243
SN - 0780312813
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - 1583
EP - 1586
BT - Proceedings
T2 - 1993 IEEE International Symposium on Circuits and Systems
Y2 - 3 May 1993 through 6 May 1993
ER -