Fast and Accurate Power Estimation for Application-Specific Instruction Set Processors using FPGA Emulation

Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review

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OriginalspracheEnglisch
Titel des SammelwerksProceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing
UntertitelDASIP
Herausgeber/-innenSophie Cerisier, Adam Morawiec
Herausgeber (Verlag)IEEE Computer Society
ISBN (elektronisch)9791092279108
PublikationsstatusVeröffentlicht - 4 Jan. 2016
Veranstaltung2015 Conference on Design and Architectures for Signal and Image Processing, DASIP - Cracow, Polen
Dauer: 23 Sept. 2015 → 25 Sept. 2015

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Fast and Accurate Power Estimation for Application-Specific Instruction Set Processors using FPGA Emulation. / Hesselbarth, Sebastian; Schewior, Gregor; Blume, Holger.
Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing: DASIP . Hrsg. / Sophie Cerisier; Adam Morawiec. IEEE Computer Society, 2016.

Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review

Hesselbarth, S, Schewior, G & Blume, H 2016, Fast and Accurate Power Estimation for Application-Specific Instruction Set Processors using FPGA Emulation. in S Cerisier & A Morawiec (Hrsg.), Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing: DASIP . IEEE Computer Society, 2015 Conference on Design and Architectures for Signal and Image Processing, DASIP , Cracow, Polen, 23 Sept. 2015. https://doi.org/10.1109/DASIP.2015.7367249
Hesselbarth, S., Schewior, G., & Blume, H. (2016). Fast and Accurate Power Estimation for Application-Specific Instruction Set Processors using FPGA Emulation. In S. Cerisier, & A. Morawiec (Hrsg.), Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing: DASIP IEEE Computer Society. https://doi.org/10.1109/DASIP.2015.7367249
Hesselbarth S, Schewior G, Blume H. Fast and Accurate Power Estimation for Application-Specific Instruction Set Processors using FPGA Emulation. in Cerisier S, Morawiec A, Hrsg., Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing: DASIP . IEEE Computer Society. 2016 doi: 10.1109/DASIP.2015.7367249
Hesselbarth, Sebastian ; Schewior, Gregor ; Blume, Holger. / Fast and Accurate Power Estimation for Application-Specific Instruction Set Processors using FPGA Emulation. Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing: DASIP . Hrsg. / Sophie Cerisier ; Adam Morawiec. IEEE Computer Society, 2016.
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@inproceedings{1de89e73abcd49e6a936f5510ca8350e,
title = "Fast and Accurate Power Estimation for Application-Specific Instruction Set Processors using FPGA Emulation",
keywords = "Emulation, Estimation, Field programmable gate arrays, Hardware, Power demand, Program processors, Registers",
author = "Sebastian Hesselbarth and Gregor Schewior and Holger Blume",
year = "2016",
month = jan,
day = "4",
doi = "10.1109/DASIP.2015.7367249",
language = "English",
editor = "Sophie Cerisier and Adam Morawiec",
booktitle = "Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing",
publisher = "IEEE Computer Society",
address = "United States",
note = "2015 Conference on Design and Architectures for Signal and Image Processing, DASIP ; Conference date: 23-09-2015 Through 25-09-2015",

}

Download

TY - GEN

T1 - Fast and Accurate Power Estimation for Application-Specific Instruction Set Processors using FPGA Emulation

AU - Hesselbarth, Sebastian

AU - Schewior, Gregor

AU - Blume, Holger

PY - 2016/1/4

Y1 - 2016/1/4

KW - Emulation

KW - Estimation

KW - Field programmable gate arrays

KW - Hardware

KW - Power demand

KW - Program processors

KW - Registers

UR - http://www.scopus.com/inward/record.url?scp=84959902902&partnerID=8YFLogxK

U2 - 10.1109/DASIP.2015.7367249

DO - 10.1109/DASIP.2015.7367249

M3 - Conference contribution

AN - SCOPUS:84959902902

BT - Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing

A2 - Cerisier, Sophie

A2 - Morawiec, Adam

PB - IEEE Computer Society

T2 - 2015 Conference on Design and Architectures for Signal and Image Processing, DASIP

Y2 - 23 September 2015 through 25 September 2015

ER -

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