Details
| Originalsprache | Englisch |
|---|---|
| Titel des Sammelwerks | Proceedings - 2024 IEEE 35th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2024 |
| Seiten | 176-183 |
| Seitenumfang | 8 |
| ISBN (elektronisch) | 979-8-3503-4963-4 |
| Publikationsstatus | Veröffentlicht - 2024 |
Publikationsreihe
| Name | EEE International Conference on Application-Specific Systems, Architectures, and Processors |
|---|---|
| ISSN (Print) | 2160-0511 |
| ISSN (elektronisch) | 2160-052X |
Abstract
As the number of individuals experiencing hearing problems rises, research in this area is increasing. In particular, algorithms for enhancing sound quality are becoming more advanced. However, the energy consumption of hearing aids is restricted to a few milliwatts. New hearing aid processors and hardware must be developed to tackle this issue. Therefore, this paper presents and evaluates custom hardware units for hearing aids suitable for flexible fixed-point formats. The units are added to the instruction set architecture (ISA) of a Tensilica Fusion G6. This is one of two high-level programmable application-specific instruction-set processors (ASIP) integrated into the Smart Hearing Aid Processor (SmartHeaP), a hearing aid system-on-chip (SoC) fabricated in 22nm fully depleted silicon on insulator (FD-SOI) technology. As many audio algorithms operate in the frequency domain, complex-domain units like a complex multiply-accumulate (CMAC) unit are introduced first. Additionally, coordinate rotation digital computer (CORDIC) operations have been added to speed up nonlinear functions such as logarithms, another function frequently used in hearing aid applications. The implemented extensions are integrated into a MATLAB fixed-point framework to simplify access to the ISA extensions for algorithm developers. It automatically generates fixed-point C code with direct access to the added instructions, reducing development time and complexity. Integrating the seven proposed instructions with corresponding register files increases the core area by 20% or 0.065 mm 2in a 22nm front-end synthesis. On the other hand, these extensions reduce the cycle count for two evaluated hearing aid algorithms, a beamformer and a loudness compensator, by 93% and 38%. A reduction of up to 84% is achieved for standalone mathematical functions, like logarithmic calculations. These performance improvements directly translate into power savings by allowing a reduced clock frequency.
ASJC Scopus Sachgebiete
- Informatik (insg.)
- Hardware und Architektur
- Informatik (insg.)
- Computernetzwerke und -kommunikation
Ziele für nachhaltige Entwicklung
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- Apa
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Proceedings - 2024 IEEE 35th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2024. 2024. S. 176-183 (EEE International Conference on Application-Specific Systems, Architectures, and Processors).
Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review
}
TY - GEN
T1 - Enhancing a Hearing Aid Processor with ISA Extensions Supporting Flexible Fixed-Point Formats
AU - Karrenbauer, Jens
AU - Schönewald, Sven
AU - Klein, Simon
AU - Blume, Holger
N1 - Publisher Copyright: © 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - As the number of individuals experiencing hearing problems rises, research in this area is increasing. In particular, algorithms for enhancing sound quality are becoming more advanced. However, the energy consumption of hearing aids is restricted to a few milliwatts. New hearing aid processors and hardware must be developed to tackle this issue. Therefore, this paper presents and evaluates custom hardware units for hearing aids suitable for flexible fixed-point formats. The units are added to the instruction set architecture (ISA) of a Tensilica Fusion G6. This is one of two high-level programmable application-specific instruction-set processors (ASIP) integrated into the Smart Hearing Aid Processor (SmartHeaP), a hearing aid system-on-chip (SoC) fabricated in 22nm fully depleted silicon on insulator (FD-SOI) technology. As many audio algorithms operate in the frequency domain, complex-domain units like a complex multiply-accumulate (CMAC) unit are introduced first. Additionally, coordinate rotation digital computer (CORDIC) operations have been added to speed up nonlinear functions such as logarithms, another function frequently used in hearing aid applications. The implemented extensions are integrated into a MATLAB fixed-point framework to simplify access to the ISA extensions for algorithm developers. It automatically generates fixed-point C code with direct access to the added instructions, reducing development time and complexity. Integrating the seven proposed instructions with corresponding register files increases the core area by 20% or 0.065 mm 2in a 22nm front-end synthesis. On the other hand, these extensions reduce the cycle count for two evaluated hearing aid algorithms, a beamformer and a loudness compensator, by 93% and 38%. A reduction of up to 84% is achieved for standalone mathematical functions, like logarithmic calculations. These performance improvements directly translate into power savings by allowing a reduced clock frequency.
AB - As the number of individuals experiencing hearing problems rises, research in this area is increasing. In particular, algorithms for enhancing sound quality are becoming more advanced. However, the energy consumption of hearing aids is restricted to a few milliwatts. New hearing aid processors and hardware must be developed to tackle this issue. Therefore, this paper presents and evaluates custom hardware units for hearing aids suitable for flexible fixed-point formats. The units are added to the instruction set architecture (ISA) of a Tensilica Fusion G6. This is one of two high-level programmable application-specific instruction-set processors (ASIP) integrated into the Smart Hearing Aid Processor (SmartHeaP), a hearing aid system-on-chip (SoC) fabricated in 22nm fully depleted silicon on insulator (FD-SOI) technology. As many audio algorithms operate in the frequency domain, complex-domain units like a complex multiply-accumulate (CMAC) unit are introduced first. Additionally, coordinate rotation digital computer (CORDIC) operations have been added to speed up nonlinear functions such as logarithms, another function frequently used in hearing aid applications. The implemented extensions are integrated into a MATLAB fixed-point framework to simplify access to the ISA extensions for algorithm developers. It automatically generates fixed-point C code with direct access to the added instructions, reducing development time and complexity. Integrating the seven proposed instructions with corresponding register files increases the core area by 20% or 0.065 mm 2in a 22nm front-end synthesis. On the other hand, these extensions reduce the cycle count for two evaluated hearing aid algorithms, a beamformer and a loudness compensator, by 93% and 38%. A reduction of up to 84% is achieved for standalone mathematical functions, like logarithmic calculations. These performance improvements directly translate into power savings by allowing a reduced clock frequency.
KW - CMAC
KW - CORDIC
KW - ISA extension
KW - MATLAB
KW - SmartHeaP
KW - Tensilica
KW - fixed-point arithmetic
UR - http://www.scopus.com/inward/record.url?scp=85203108425&partnerID=8YFLogxK
U2 - 10.1109/asap61560.2024.00044
DO - 10.1109/asap61560.2024.00044
M3 - Conference contribution
SN - 979-8-3503-4964-1
T3 - EEE International Conference on Application-Specific Systems, Architectures, and Processors
SP - 176
EP - 183
BT - Proceedings - 2024 IEEE 35th International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2024
ER -