Efficient Emulation of Floating-Point Arithmetic on Fixed-Point SIMD Processors

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OriginalspracheEnglisch
Titel des SammelwerksIEEE International Workshop on Signal Processing Systems
UntertitelSiPS
Herausgeber (Verlag)IEEE Computer Society
Seiten254-259
Seitenumfang6
ISBN (elektronisch)9781509033614
ISBN (Print)978-1-5090-3362-1
PublikationsstatusVeröffentlicht - 12 Dez. 2016
Veranstaltung2016 IEEE International Workshop on Signal Processing Systems, SiPS 2016 - Dallas, USA / Vereinigte Staaten
Dauer: 26 Okt. 201628 Okt. 2016

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Efficient Emulation of Floating-Point Arithmetic on Fixed-Point SIMD Processors. / Gerlach, Lukas; Payá-Vayá, Guillermo; Blume, Holger.
IEEE International Workshop on Signal Processing Systems: SiPS. IEEE Computer Society, 2016. S. 254-259.

Publikation: Beitrag in Buch/Bericht/Sammelwerk/KonferenzbandAufsatz in KonferenzbandForschungPeer-Review

Gerlach, L, Payá-Vayá, G & Blume, H 2016, Efficient Emulation of Floating-Point Arithmetic on Fixed-Point SIMD Processors. in IEEE International Workshop on Signal Processing Systems: SiPS. IEEE Computer Society, S. 254-259, 2016 IEEE International Workshop on Signal Processing Systems, SiPS 2016, Dallas, USA / Vereinigte Staaten, 26 Okt. 2016. https://doi.org/10.1109/SiPS.2016.52
Gerlach, L., Payá-Vayá, G., & Blume, H. (2016). Efficient Emulation of Floating-Point Arithmetic on Fixed-Point SIMD Processors. In IEEE International Workshop on Signal Processing Systems: SiPS (S. 254-259). IEEE Computer Society. https://doi.org/10.1109/SiPS.2016.52
Gerlach L, Payá-Vayá G, Blume H. Efficient Emulation of Floating-Point Arithmetic on Fixed-Point SIMD Processors. in IEEE International Workshop on Signal Processing Systems: SiPS. IEEE Computer Society. 2016. S. 254-259 doi: 10.1109/SiPS.2016.52
Gerlach, Lukas ; Payá-Vayá, Guillermo ; Blume, Holger. / Efficient Emulation of Floating-Point Arithmetic on Fixed-Point SIMD Processors. IEEE International Workshop on Signal Processing Systems: SiPS. IEEE Computer Society, 2016. S. 254-259
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