Efficiency modeling for MHz DCDC converters at 40 v input voltage range

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OriginalspracheEnglisch
Seiten (von - bis)111-115
Seitenumfang5
FachzeitschriftAdvances in Radio Science
Jahrgang12
PublikationsstatusVeröffentlicht - 10 Nov. 2014
Extern publiziertJa

Abstract

Size and cost of a switched mode power supply can be reduced by increasing the switching frequency. This leads especially at a high input voltage to a decreasing efficiency caused by switching losses. Conventional calculations are not suitable to predict the efficiency as parasitic capacitances have a significant loss contribution. This paper presents an analytical efficiency model which considers parasitic capacitances separately and calculates the power loss contribution of each capacitance to any resistive element. The proposed model is utilized for efficiency optimization of converters with switching frequencies > 10 MHz and input voltages up to 40 V. For experimental evaluation a DCDC converter was manufactured in a 180 nm HV BiCMOS technology. The model matches a transistor level simulation and measurement results with an accuracy better than 3.5 %. The accuracy of the parasitic capacitances of the high voltage transistor determines the overall accuracy of the efficiency model. Experimental capacitor measurements can be fed into the model. Based on the model, different architectures have been studied.

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Efficiency modeling for MHz DCDC converters at 40 v input voltage range. / Wittmann, J.; Seidel, A.; Wicht, B.
in: Advances in Radio Science, Jahrgang 12, 10.11.2014, S. 111-115.

Publikation: Beitrag in FachzeitschriftArtikelForschungPeer-Review

Wittmann J, Seidel A, Wicht B. Efficiency modeling for MHz DCDC converters at 40 v input voltage range. Advances in Radio Science. 2014 Nov 10;12:111-115. doi: 10.5194/ars-12-111-2014
Wittmann, J. ; Seidel, A. ; Wicht, B. / Efficiency modeling for MHz DCDC converters at 40 v input voltage range. in: Advances in Radio Science. 2014 ; Jahrgang 12. S. 111-115.
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