Details
| Originalsprache | Englisch |
|---|---|
| Seiten (von - bis) | 1365-1369 |
| Seitenumfang | 5 |
| Fachzeitschrift | Microelectronics reliability |
| Jahrgang | 53 |
| Ausgabenummer | 9-11 |
| Publikationsstatus | Veröffentlicht - Sept. 2013 |
Abstract
At the moment the miniaturisation of integrated circuits for consumer electronics means to decrease the size of Cu interconnects below 100 nm, while a lifetime of 3-5 years has to be guaranteed. For industrial and automotive applications wider Al interconnects (∼350 nm) are used, but an extreme low rate of failures (0.1 ppm) has to be reached to produce reliable end-products including dozens of components. A further progress in the development of high-end electronics and more complex industrial products needs a better prediction of possible failure mechanism and the related time to failure of the chosen technology. This investigation is focused on migration induced void formation and combines the results of process simulations, for the back end of line, (intrinsic pre-stress) with the dynamic simulation of the migration induced material movement in the interconnects. To minimise the gap between idealized simulations and reliability tests the grain structure of the Al and Cu lines, the interaction between electromigration and the mass flux due concentration gradients, as well as the different transport mechanism for grain boundary and interface diffusion were taken into account. For the surrounding metal of existing voids specific activation energies in dependence on the crystal orientation of the metal surfaces were given. As result a prediction of the point of failure and the void formation process will be given for the chosen back-end technologies.
ASJC Scopus Sachgebiete
- Werkstoffwissenschaften (insg.)
- Elektronische, optische und magnetische Materialien
- Physik und Astronomie (insg.)
- Atom- und Molekularphysik sowie Optik
- Physik und Astronomie (insg.)
- Physik der kondensierten Materie
- Ingenieurwesen (insg.)
- Sicherheit, Risiko, Zuverlässigkeit und Qualität
- Werkstoffwissenschaften (insg.)
- Oberflächen, Beschichtungen und Folien
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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in: Microelectronics reliability, Jahrgang 53, Nr. 9-11, 09.2013, S. 1365-1369.
Publikation: Beitrag in Fachzeitschrift › Artikel › Forschung › Peer-Review
}
TY - JOUR
T1 - Dynamic simulation of migration induced failure mechanism in integrated circuit interconnects
AU - Moujbani, Aymen
AU - Kludt, Jörg
AU - Weide-Zaage, Kirsten
AU - Ackermann, Markus
AU - Hein, Verena
AU - Meinshausen, Lutz
N1 - Copyright: Copyright 2013 Elsevier B.V., All rights reserved.
PY - 2013/9
Y1 - 2013/9
N2 - At the moment the miniaturisation of integrated circuits for consumer electronics means to decrease the size of Cu interconnects below 100 nm, while a lifetime of 3-5 years has to be guaranteed. For industrial and automotive applications wider Al interconnects (∼350 nm) are used, but an extreme low rate of failures (0.1 ppm) has to be reached to produce reliable end-products including dozens of components. A further progress in the development of high-end electronics and more complex industrial products needs a better prediction of possible failure mechanism and the related time to failure of the chosen technology. This investigation is focused on migration induced void formation and combines the results of process simulations, for the back end of line, (intrinsic pre-stress) with the dynamic simulation of the migration induced material movement in the interconnects. To minimise the gap between idealized simulations and reliability tests the grain structure of the Al and Cu lines, the interaction between electromigration and the mass flux due concentration gradients, as well as the different transport mechanism for grain boundary and interface diffusion were taken into account. For the surrounding metal of existing voids specific activation energies in dependence on the crystal orientation of the metal surfaces were given. As result a prediction of the point of failure and the void formation process will be given for the chosen back-end technologies.
AB - At the moment the miniaturisation of integrated circuits for consumer electronics means to decrease the size of Cu interconnects below 100 nm, while a lifetime of 3-5 years has to be guaranteed. For industrial and automotive applications wider Al interconnects (∼350 nm) are used, but an extreme low rate of failures (0.1 ppm) has to be reached to produce reliable end-products including dozens of components. A further progress in the development of high-end electronics and more complex industrial products needs a better prediction of possible failure mechanism and the related time to failure of the chosen technology. This investigation is focused on migration induced void formation and combines the results of process simulations, for the back end of line, (intrinsic pre-stress) with the dynamic simulation of the migration induced material movement in the interconnects. To minimise the gap between idealized simulations and reliability tests the grain structure of the Al and Cu lines, the interaction between electromigration and the mass flux due concentration gradients, as well as the different transport mechanism for grain boundary and interface diffusion were taken into account. For the surrounding metal of existing voids specific activation energies in dependence on the crystal orientation of the metal surfaces were given. As result a prediction of the point of failure and the void formation process will be given for the chosen back-end technologies.
UR - http://www.scopus.com/inward/record.url?scp=84886882157&partnerID=8YFLogxK
U2 - 10.1016/j.microrel.2013.07.097
DO - 10.1016/j.microrel.2013.07.097
M3 - Article
AN - SCOPUS:84886882157
VL - 53
SP - 1365
EP - 1369
JO - Microelectronics reliability
JF - Microelectronics reliability
SN - 0026-2714
IS - 9-11
ER -