Details
| Originalsprache | Englisch |
|---|---|
| Titel des Sammelwerks | Proceedings 20th IEEE International Parallel & Distributed Processing Symposium |
| Herausgeber (Verlag) | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (Print) | 1424400546 |
| Publikationsstatus | Veröffentlicht - 26 Juni 2006 |
| Extern publiziert | Ja |
| Veranstaltung | 20th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2006 - Rhodes Island, Griechenland Dauer: 25 Apr. 2006 → 29 Apr. 2006 |
Abstract
This paper investigates the implementation of a number of circuits used to perform a high speed closest value match lookup. The design is targeted particularly for use in a search trie, as used in various networking lookup applications, but can be applied to many other areas where such a match is required. A range of different designs have been considered and implemented on FPGA. A detailed description of the architectures investigated is followed by an analysis of the synthesis results.
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Proceedings 20th IEEE International Parallel & Distributed Processing Symposium. Institute of Electrical and Electronics Engineers Inc., 2006.
Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review
}
TY - GEN
T1 - Design and analysis of matching circuit architectures for a closest match lookup
AU - McLaughlin, Kieran
AU - Kupzog, Friederich
AU - Blume, Holger
AU - Sezer, Sakir
AU - Noll, Tobias
AU - McCanny, John
PY - 2006/6/26
Y1 - 2006/6/26
N2 - This paper investigates the implementation of a number of circuits used to perform a high speed closest value match lookup. The design is targeted particularly for use in a search trie, as used in various networking lookup applications, but can be applied to many other areas where such a match is required. A range of different designs have been considered and implemented on FPGA. A detailed description of the architectures investigated is followed by an analysis of the synthesis results.
AB - This paper investigates the implementation of a number of circuits used to perform a high speed closest value match lookup. The design is targeted particularly for use in a search trie, as used in various networking lookup applications, but can be applied to many other areas where such a match is required. A range of different designs have been considered and implemented on FPGA. A detailed description of the architectures investigated is followed by an analysis of the synthesis results.
UR - http://www.scopus.com/inward/record.url?scp=33847167641&partnerID=8YFLogxK
U2 - 10.1109/IPDPS.2006.1639481
DO - 10.1109/IPDPS.2006.1639481
M3 - Conference contribution
AN - SCOPUS:33847167641
SN - 1424400546
BT - Proceedings 20th IEEE International Parallel & Distributed Processing Symposium
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 20th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2006
Y2 - 25 April 2006 through 29 April 2006
ER -