Details
Originalsprache | Englisch |
---|---|
Aufsatznummer | 655985 |
Seiten (von - bis) | 953-954 |
Seitenumfang | 2 |
Fachzeitschrift | Proceedings -Design, Automation and Test in Europe, DATE |
Publikationsstatus | Veröffentlicht - 1998 |
Veranstaltung | Design, Automation and Test in Europe, DATE 1998 - Paris, Frankreich Dauer: 23 Feb. 1998 → 26 Feb. 1998 |
Abstract
Interconnects must not only be analyzed with regard to opens and shorts but also with regard to the signal delays. Up to now, opens and shorts in bus systems on boards have been tested using boundary scan, mostly neglecting delay test. In addition, it has to be considered that the signal delay (i.e. the time when the signal crosses the switching threshold of the following gate) on a certain line within a bus system depends on the set of input signals of all bus lines. Furthermore, hazards can occur due to coupling between bus lines which can lead to an incorrect function of the whole circuit. Different interconnect systems with different test patterns have been analyzed and the results for 0.10 μm technology will be given. The geometric data for the interconnects in 0.10 μm technology has been derived or directly extracted from the SIA-Roadmap. With this data the line parameters for the simulation of the interconnects have been calculated with the help of a tool which takes into account conducting substrates.
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in: Proceedings -Design, Automation and Test in Europe, DATE, 1998, S. 953-954.
Publikation: Beitrag in Fachzeitschrift › Konferenzaufsatz in Fachzeitschrift › Forschung › Peer-Review
}
TY - JOUR
T1 - Core interconnect testing hazards
AU - Nordholz, Petra
AU - Grabinski, Hartmut
AU - Treytnar, Dieter
AU - Otterstedt, Jan
AU - Niggemeyer, Dirk
AU - Arz, Uwe
AU - Williams, T. W.
PY - 1998
Y1 - 1998
N2 - Interconnects must not only be analyzed with regard to opens and shorts but also with regard to the signal delays. Up to now, opens and shorts in bus systems on boards have been tested using boundary scan, mostly neglecting delay test. In addition, it has to be considered that the signal delay (i.e. the time when the signal crosses the switching threshold of the following gate) on a certain line within a bus system depends on the set of input signals of all bus lines. Furthermore, hazards can occur due to coupling between bus lines which can lead to an incorrect function of the whole circuit. Different interconnect systems with different test patterns have been analyzed and the results for 0.10 μm technology will be given. The geometric data for the interconnects in 0.10 μm technology has been derived or directly extracted from the SIA-Roadmap. With this data the line parameters for the simulation of the interconnects have been calculated with the help of a tool which takes into account conducting substrates.
AB - Interconnects must not only be analyzed with regard to opens and shorts but also with regard to the signal delays. Up to now, opens and shorts in bus systems on boards have been tested using boundary scan, mostly neglecting delay test. In addition, it has to be considered that the signal delay (i.e. the time when the signal crosses the switching threshold of the following gate) on a certain line within a bus system depends on the set of input signals of all bus lines. Furthermore, hazards can occur due to coupling between bus lines which can lead to an incorrect function of the whole circuit. Different interconnect systems with different test patterns have been analyzed and the results for 0.10 μm technology will be given. The geometric data for the interconnects in 0.10 μm technology has been derived or directly extracted from the SIA-Roadmap. With this data the line parameters for the simulation of the interconnects have been calculated with the help of a tool which takes into account conducting substrates.
UR - http://www.scopus.com/inward/record.url?scp=84893727824&partnerID=8YFLogxK
U2 - 10.1109/DATE.1998.655985
DO - 10.1109/DATE.1998.655985
M3 - Conference article
AN - SCOPUS:84893727824
SP - 953
EP - 954
JO - Proceedings -Design, Automation and Test in Europe, DATE
JF - Proceedings -Design, Automation and Test in Europe, DATE
SN - 1530-1591
M1 - 655985
T2 - Design, Automation and Test in Europe, DATE 1998
Y2 - 23 February 1998 through 26 February 1998
ER -