Co-processor architecture for MPEG-4 main profile visual compositing

Publikation: Beitrag in Fachzeitschrift › Artikel › Forschung › Peer-Review

Autoren

  • M. Berekovic
  • P. Pirsch
  • T. Selinger
  • K. I. Wels
  • C. Miro
  • A. Lafage
  • C. Heer
  • G. Ghigo

Organisationseinheiten

Externe Organisationen

  • Fraunhofer-Institut für Nachrichtentechnik, Heinrich-Hertz-Institut (HHI)
  • Télécom ParisTech
  • Siemens AG
  • Centro Studi e Laboratori Telecomunicazioni (CSELT)
Forschungs-netzwerk anzeigen

Details

OriginalspracheEnglisch
Seiten (von - bis)II-180-II-183
FachzeitschriftProceedings - IEEE International Symposium on Circuits and Systems
Jahrgang2
PublikationsstatusVeröffentlicht - 2000

Abstract

The TANGRAM VLSI co-processor is intended to assist existing MPEG-4 video-decoders to perform the computation intensive final step of MPEG-4 video decoding: compositing of scenes at the display. TANGRAM consists of a RISC control processor and multiple powerful arithmetic units that perform rendering calculations directly in hardware. This hybrid architecture enables adaptation to changes in algorithms or support for different video-formats in software. Communication to a host CPU and video decoding hardware is done via the very common Pl-bus on-chip interface. TANGRAM directly interfaces with the ITU-R601/656 digital video output. VHDL implementation and synthesis for a 0.35 μ standard-cell library provide an estimate of 100 MHz achievable clock-frequency (worst-case), 52 mm2 overall area and 1 Watt power dissipation. TANGRAM has sufficient performance for rendering of MPEG-4 Main ProfileLayer3 scenes (CCIR).

ASJC Scopus Sachgebiete

Zitieren

Co-processor architecture for MPEG-4 main profile visual compositing. / Berekovic, M.; Pirsch, P.; Selinger, T. et al.
in: Proceedings - IEEE International Symposium on Circuits and Systems, Jahrgang 2, 2000, S. II-180-II-183.

Publikation: Beitrag in Fachzeitschrift › Artikel › Forschung › Peer-Review

Berekovic, M, Pirsch, P, Selinger, T, Wels, KI, Miro, C, Lafage, A, Heer, C & Ghigo, G 2000, 'Co-processor architecture for MPEG-4 main profile visual compositing', Proceedings - IEEE International Symposium on Circuits and Systems, Jg. 2, S. II-180-II-183. https://doi.org/10.1109/ISCAS.2000.856288
Berekovic, M., Pirsch, P., Selinger, T., Wels, K. I., Miro, C., Lafage, A., Heer, C., & Ghigo, G. (2000). Co-processor architecture for MPEG-4 main profile visual compositing. Proceedings - IEEE International Symposium on Circuits and Systems, 2, II-180-II-183. https://doi.org/10.1109/ISCAS.2000.856288
Berekovic M, Pirsch P, Selinger T, Wels KI, Miro C, Lafage A et al. Co-processor architecture for MPEG-4 main profile visual compositing. Proceedings - IEEE International Symposium on Circuits and Systems. 2000;2:II-180-II-183. doi: 10.1109/ISCAS.2000.856288
Berekovic, M. ; Pirsch, P. ; Selinger, T. et al. / Co-processor architecture for MPEG-4 main profile visual compositing. in: Proceedings - IEEE International Symposium on Circuits and Systems. 2000 ; Jahrgang 2. S. II-180-II-183.
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