Details
| Originalsprache | Englisch |
|---|---|
| Titel des Sammelwerks | 2016 IEEE Applied Power Electronics Conference and Exposition, APEC 2016 |
| Herausgeber (Verlag) | Institute of Electrical and Electronics Engineers Inc. |
| Seiten | 3172-3179 |
| Seitenumfang | 8 |
| ISBN (elektronisch) | 9781467383936 |
| Publikationsstatus | Veröffentlicht - 10 Mai 2016 |
| Veranstaltung | 31st Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2016 - Long Beach, USA / Vereinigte Staaten Dauer: 20 März 2016 → 24 März 2016 |
Publikationsreihe
| Name | Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC |
|---|---|
| Band | 2016-May |
Abstract
This paper presents a novel approach to compensate the voltage error due to switching dead times in voltage-fed inverters using a field-programmable gate array (FPGA) and current oversampling. The FPGA controls an analog-to-digital (AD) converter which operates at a high conversion rate and processes numerous current samples taken at equidistant time steps within each pulse width modulation (PWM) period. The FPGA also generates the inverter's PWM modulation. As phase currents at an inductive load can be approximated by piecewise linear time functions during each switching state of the inverter, the FPGA interpolates the current slopes using a linear least mean squares regression. Based on this regression, a predictor structure in the FPGA predicts the phase current right at the beginning of the switching dead time. The predictor structure can be computed almost instantaneously due to parallel data processing. Based on the estimated phase current, the FPGA uses a lookup table, depending on current and DC link voltage, to correct an upcoming switching instant in order to compensate for the dead-time effect. Depending on current polarity and magnitude, the lookup table stores the respective compensation times for the upcoming switching instants. The lookup table is the result of an offline commissioning process.
ASJC Scopus Sachgebiete
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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2016 IEEE Applied Power Electronics Conference and Exposition, APEC 2016. Institute of Electrical and Electronics Engineers Inc., 2016. S. 3172-3179 7468318 (Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC; Band 2016-May).
Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review
}
TY - GEN
T1 - Compensation of switching dead-time effects in voltage-fed PWM inverters using FPGA-based current oversampling
AU - Weber, Bastian
AU - Brandt, Tobias
AU - Mertens, Axel
PY - 2016/5/10
Y1 - 2016/5/10
N2 - This paper presents a novel approach to compensate the voltage error due to switching dead times in voltage-fed inverters using a field-programmable gate array (FPGA) and current oversampling. The FPGA controls an analog-to-digital (AD) converter which operates at a high conversion rate and processes numerous current samples taken at equidistant time steps within each pulse width modulation (PWM) period. The FPGA also generates the inverter's PWM modulation. As phase currents at an inductive load can be approximated by piecewise linear time functions during each switching state of the inverter, the FPGA interpolates the current slopes using a linear least mean squares regression. Based on this regression, a predictor structure in the FPGA predicts the phase current right at the beginning of the switching dead time. The predictor structure can be computed almost instantaneously due to parallel data processing. Based on the estimated phase current, the FPGA uses a lookup table, depending on current and DC link voltage, to correct an upcoming switching instant in order to compensate for the dead-time effect. Depending on current polarity and magnitude, the lookup table stores the respective compensation times for the upcoming switching instants. The lookup table is the result of an offline commissioning process.
AB - This paper presents a novel approach to compensate the voltage error due to switching dead times in voltage-fed inverters using a field-programmable gate array (FPGA) and current oversampling. The FPGA controls an analog-to-digital (AD) converter which operates at a high conversion rate and processes numerous current samples taken at equidistant time steps within each pulse width modulation (PWM) period. The FPGA also generates the inverter's PWM modulation. As phase currents at an inductive load can be approximated by piecewise linear time functions during each switching state of the inverter, the FPGA interpolates the current slopes using a linear least mean squares regression. Based on this regression, a predictor structure in the FPGA predicts the phase current right at the beginning of the switching dead time. The predictor structure can be computed almost instantaneously due to parallel data processing. Based on the estimated phase current, the FPGA uses a lookup table, depending on current and DC link voltage, to correct an upcoming switching instant in order to compensate for the dead-time effect. Depending on current polarity and magnitude, the lookup table stores the respective compensation times for the upcoming switching instants. The lookup table is the result of an offline commissioning process.
KW - current oversampling
KW - Dead-time effect
KW - FPGA-based control
KW - inverter nonlinearity
UR - http://www.scopus.com/inward/record.url?scp=84973596264&partnerID=8YFLogxK
U2 - 10.1109/APEC.2016.7468318
DO - 10.1109/APEC.2016.7468318
M3 - Conference contribution
AN - SCOPUS:84973596264
T3 - Conference Proceedings - IEEE Applied Power Electronics Conference and Exposition - APEC
SP - 3172
EP - 3179
BT - 2016 IEEE Applied Power Electronics Conference and Exposition, APEC 2016
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 31st Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2016
Y2 - 20 March 2016 through 24 March 2016
ER -