Details
Originalsprache | Englisch |
---|---|
Seiten (von - bis) | 1968-1971 |
Seitenumfang | 4 |
Fachzeitschrift | Microelectronic engineering |
Jahrgang | 84 |
Ausgabenummer | 9-10 |
Frühes Online-Datum | 30 Mai 2007 |
Publikationsstatus | Veröffentlicht - Sept. 2007 |
Abstract
Charge trapping in ultrathin high-k Gd2O3 dielectric leading to appearance of hysteresis in C-V curves is studied by capacitance-voltage and current-voltage techniques. It was shown that the large leakage current at a negative gate voltage causes the generation of the positive charge in the dielectric layer, resulting in the respective shift of the C-V curve. The capture cross-section of the hole traps is around 2 × 10-20 cm2. The distribution of the interface states was measured by conductance technique showing the concentration up to 7.5 × 1012 eV-1 cm-2 near the valence band edge.
ASJC Scopus Sachgebiete
- Werkstoffwissenschaften (insg.)
- Elektronische, optische und magnetische Materialien
- Physik und Astronomie (insg.)
- Atom- und Molekularphysik sowie Optik
- Physik und Astronomie (insg.)
- Physik der kondensierten Materie
- Werkstoffwissenschaften (insg.)
- Oberflächen, Beschichtungen und Folien
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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in: Microelectronic engineering, Jahrgang 84, Nr. 9-10, 09.2007, S. 1968-1971.
Publikation: Beitrag in Fachzeitschrift › Artikel › Forschung › Peer-Review
}
TY - JOUR
T1 - Charge trapping in ultrathin Gd2O3 high-k dielectric
AU - Nazarov, A. N.
AU - Gomeniuk, Y. V.
AU - Gomeniuk, Y. Y.
AU - Gottlob, H. D.B.
AU - Schmidt, M.
AU - Lemme, M. C.
AU - Czernohorsky, M.
AU - Osten, H. J.
N1 - Funding Information: This work has been partly funded by the European Commission under the frame of the Network of Excellence “SINANO” (Silicon-based Nanodevices, IST-506844) and the German Federal Ministry of Education and Research (BMBF) in the “KrisMOS” project (01M3142).
PY - 2007/9
Y1 - 2007/9
N2 - Charge trapping in ultrathin high-k Gd2O3 dielectric leading to appearance of hysteresis in C-V curves is studied by capacitance-voltage and current-voltage techniques. It was shown that the large leakage current at a negative gate voltage causes the generation of the positive charge in the dielectric layer, resulting in the respective shift of the C-V curve. The capture cross-section of the hole traps is around 2 × 10-20 cm2. The distribution of the interface states was measured by conductance technique showing the concentration up to 7.5 × 1012 eV-1 cm-2 near the valence band edge.
AB - Charge trapping in ultrathin high-k Gd2O3 dielectric leading to appearance of hysteresis in C-V curves is studied by capacitance-voltage and current-voltage techniques. It was shown that the large leakage current at a negative gate voltage causes the generation of the positive charge in the dielectric layer, resulting in the respective shift of the C-V curve. The capture cross-section of the hole traps is around 2 × 10-20 cm2. The distribution of the interface states was measured by conductance technique showing the concentration up to 7.5 × 1012 eV-1 cm-2 near the valence band edge.
KW - Charge trapping
KW - GdO
KW - High-k dielectric
KW - Rare earth oxide
UR - http://www.scopus.com/inward/record.url?scp=34248661852&partnerID=8YFLogxK
U2 - 10.1016/j.mee.2007.04.136
DO - 10.1016/j.mee.2007.04.136
M3 - Article
AN - SCOPUS:34248661852
VL - 84
SP - 1968
EP - 1971
JO - Microelectronic engineering
JF - Microelectronic engineering
SN - 0167-9317
IS - 9-10
ER -