Architecture of an image rendering co-processor for MPEG-4 systems

Publikation: Konferenzbeitrag › Paper › Forschung › Peer-Review

Autoren

  • M. Berekovic
  • P. Pirsch
  • T. Selinger
  • K. I. Wels
  • C. Miro
  • A. Lafage
  • C. Heer
  • G. Ghigo

Organisationseinheiten

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Details

OriginalspracheEnglisch
Seiten15-24
Seitenumfang10
PublikationsstatusVeröffentlicht - 2000
Veranstaltung2000 IEEE International Conference on Application-Specific Systems, Architectures, and Processors - Boston, MA, USA
Dauer: 10 Juli 2000 → 12 Juli 2000

Konferenz

Konferenz2000 IEEE International Conference on Application-Specific Systems, Architectures, and Processors
OrtBoston, MA, USA
Zeitraum10 Juli 2000 → 12 Juli 2000

Abstract

The TANGRAM VLSI co-processor is intended as a building block for use in system-on-chip (SOC) designs for the versatile MPEG-4 multimedia standard. It is designed to perform the computation intensive final step of MPEG-4 video decoding: compositing of scenes at the display. This includes warping and alpha blending of multiple full-screen video textures in real-time. TANGRAM consists of a RISC control processor and multiple powerful arithmetic units that perform rendering calculations directly in hardware. This hybrid architecture enables adaptation to changes in algorithms or software support for different video-formats. Computation to a host CPU and video decoding hardware is done via the very common PI-bus on-chip interface. TANGRAM directly interfaces with the ITU-R601/656 digital video output. VHDL implementation and synthesis for a 0.35 μ standard-cell library provide an estimate of 100 MHz achievable clock-frequency (worst-case), 52 mm2 overall area and 1 Watt power dissipation. TANGRAM has sufficient performance for rendering of MPEG-4 Main ProfileLayer3 scenes (CCIR).

ASJC Scopus Sachgebiete

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Architecture of an image rendering co-processor for MPEG-4 systems. / Berekovic, M.; Pirsch, P.; Selinger, T. et al.
2000. 15-24 Beitrag in 2000 IEEE International Conference on Application-Specific Systems, Architectures, and Processors, Boston, MA, USA.

Publikation: Konferenzbeitrag › Paper › Forschung › Peer-Review

Berekovic, M, Pirsch, P, Selinger, T, Wels, KI, Miro, C, Lafage, A, Heer, C & Ghigo, G 2000, 'Architecture of an image rendering co-processor for MPEG-4 systems', Beitrag in 2000 IEEE International Conference on Application-Specific Systems, Architectures, and Processors, Boston, MA, USA, 10 Juli 2000 - 12 Juli 2000 S. 15-24.
Berekovic, M., Pirsch, P., Selinger, T., Wels, K. I., Miro, C., Lafage, A., Heer, C., & Ghigo, G. (2000). Architecture of an image rendering co-processor for MPEG-4 systems. 15-24. Beitrag in 2000 IEEE International Conference on Application-Specific Systems, Architectures, and Processors, Boston, MA, USA.
Berekovic M, Pirsch P, Selinger T, Wels KI, Miro C, Lafage A et al.. Architecture of an image rendering co-processor for MPEG-4 systems. 2000. Beitrag in 2000 IEEE International Conference on Application-Specific Systems, Architectures, and Processors, Boston, MA, USA.
Berekovic, M. ; Pirsch, P. ; Selinger, T. et al. / Architecture of an image rendering co-processor for MPEG-4 systems. Beitrag in 2000 IEEE International Conference on Application-Specific Systems, Architectures, and Processors, Boston, MA, USA.10 S.
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