Details
| Originalsprache | Englisch |
|---|---|
| Seiten (von - bis) | 274-281 |
| Seitenumfang | 8 |
| Fachzeitschrift | Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon |
| Publikationsstatus | Veröffentlicht - 1997 |
| Veranstaltung | 1997 2nd Annual IEEE International Conference on Innovative Systems in Silicon - Austin, TX, USA Dauer: 8 Okt. 1997 → 10 Okt. 1997 |
Abstract
The architecture of a MIMD-based multiprocessor system for video coding applications is presented. It consists of a number of identical bus-connected processors, each specifically adapted to video coding algorithms and equipped with an embedded DRAM for storage of image data. Each of the images to be processed is statically segmented into rectangular fields, which are distributed among the processors. The processors perform the complete set of coding or decoding tasks on the assigned portion of the image. Because each processor is equipped with sufficient memory for image storage and processing power, no additional external hardware is required. The architecture of each processor and embedded DRAM is designed for large area integration. This allows the implementation of a complex video coding system on a single chip.
ASJC Scopus Sachgebiete
- Informatik (insg.)
- Hardware und Architektur
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
- Physik und Astronomie (insg.)
- Physik der kondensierten Materie
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in: Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon, 1997, S. 274-281.
Publikation: Beitrag in Fachzeitschrift › Konferenzaufsatz in Fachzeitschrift › Forschung › Peer-Review
}
TY - JOUR
T1 - Architecture of a multiprocessor system with embedded DRAM for large area integration
AU - Herrmann, Klaus
AU - Hilgenstock, Joerg
AU - Pirsch, Peter
PY - 1997
Y1 - 1997
N2 - The architecture of a MIMD-based multiprocessor system for video coding applications is presented. It consists of a number of identical bus-connected processors, each specifically adapted to video coding algorithms and equipped with an embedded DRAM for storage of image data. Each of the images to be processed is statically segmented into rectangular fields, which are distributed among the processors. The processors perform the complete set of coding or decoding tasks on the assigned portion of the image. Because each processor is equipped with sufficient memory for image storage and processing power, no additional external hardware is required. The architecture of each processor and embedded DRAM is designed for large area integration. This allows the implementation of a complex video coding system on a single chip.
AB - The architecture of a MIMD-based multiprocessor system for video coding applications is presented. It consists of a number of identical bus-connected processors, each specifically adapted to video coding algorithms and equipped with an embedded DRAM for storage of image data. Each of the images to be processed is statically segmented into rectangular fields, which are distributed among the processors. The processors perform the complete set of coding or decoding tasks on the assigned portion of the image. Because each processor is equipped with sufficient memory for image storage and processing power, no additional external hardware is required. The architecture of each processor and embedded DRAM is designed for large area integration. This allows the implementation of a complex video coding system on a single chip.
UR - http://www.scopus.com/inward/record.url?scp=0031355552&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:0031355552
SP - 274
EP - 281
JO - Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon
JF - Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon
SN - 1063-2204
T2 - 1997 2nd Annual IEEE International Conference on Innovative Systems in Silicon
Y2 - 8 October 1997 through 10 October 1997
ER -