Details
Originalsprache | Englisch |
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Titel des Sammelwerks | Proceedings |
Untertitel | IEEE International Symposium on Circuits and Systems |
Seiten | I-157 - I-160 |
Publikationsstatus | Veröffentlicht - 1999 |
Veranstaltung | 1999 IEEE International Symposium on Circuits and Systems, ISCAS 1999 - Orlando, USA / Vereinigte Staaten Dauer: 30 Mai 1999 → 2 Juni 1999 |
Publikationsreihe
Name | Proceedings - IEEE International Symposium on Circuits and Systems |
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Band | 1 |
ISSN (Print) | 0271-4310 |
Abstract
MPEG-4 shape coding comprises Context based binary Arithmetic Encoding (CAE) as its centerpiece. The architecture of a dedicated hardware acceleration module for CAE shape decoding is presented. Synthesis with a 3LM 0.5μ CMOS library provides a size estimate of 9200 gates plus 3KB of ROM, which equals approximately 5 mm2 silicon area. The module achieves a throughput rate of 63 MPixel/s.
ASJC Scopus Sachgebiete
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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Proceedings : IEEE International Symposium on Circuits and Systems. 1999. S. I-157 - I-160 (Proceedings - IEEE International Symposium on Circuits and Systems; Band 1).
Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review
}
TY - GEN
T1 - Architecture of a hardware module for MPEG-4 shape decoding
AU - Berekovic, M.
AU - Jacob, K.
AU - Pirsch, P.
PY - 1999
Y1 - 1999
N2 - MPEG-4 shape coding comprises Context based binary Arithmetic Encoding (CAE) as its centerpiece. The architecture of a dedicated hardware acceleration module for CAE shape decoding is presented. Synthesis with a 3LM 0.5μ CMOS library provides a size estimate of 9200 gates plus 3KB of ROM, which equals approximately 5 mm2 silicon area. The module achieves a throughput rate of 63 MPixel/s.
AB - MPEG-4 shape coding comprises Context based binary Arithmetic Encoding (CAE) as its centerpiece. The architecture of a dedicated hardware acceleration module for CAE shape decoding is presented. Synthesis with a 3LM 0.5μ CMOS library provides a size estimate of 9200 gates plus 3KB of ROM, which equals approximately 5 mm2 silicon area. The module achieves a throughput rate of 63 MPixel/s.
UR - http://www.scopus.com/inward/record.url?scp=0032715810&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:0032715810
SN - 0780354729
T3 - Proceedings - IEEE International Symposium on Circuits and Systems
SP - I-157 - I-160
BT - Proceedings
T2 - 1999 IEEE International Symposium on Circuits and Systems, ISCAS 1999
Y2 - 30 May 1999 through 2 June 1999
ER -