Architecture and VLSI implementation of a RISC core for a monolithic video signal processor

Publikation: Konferenzbeitrag › Paper › Forschung › Peer-Review

Autoren

  • Klaus Herrmann
  • Martin Seifert
  • Klaus Gaedke
  • Hartwig Jeschke
  • Peter Pirsch

Organisationseinheiten

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Details

OriginalspracheEnglisch
Seiten368-377
Seitenumfang10
PublikationsstatusVeröffentlicht - 1994
Veranstaltung1994 IEEE International Workshop VLSI Signal Processing - La Jolla, CA, USA
Dauer: 26 Okt. 1994 → 28 Okt. 1994

Konferenz

Konferenz1994 IEEE International Workshop VLSI Signal Processing
OrtLa Jolla, CA, USA
Zeitraum26 Okt. 1994 → 28 Okt. 1994

Abstract

For a monolithic video signal processor a special RISC processor core has been developed. In order to achieve an efficient implementation of hybrid video coding algorithms the applied Harvard architecture with 16 bit data path is adapted to tasks like quantization, variable length coding and run length coding. The RISC processor's die size is 68.79 mm2 fabricated in a 0.8 μm CMOS technology. 4 kByte of program RAM and 512 Bytes of Data Memory are implemented on chip. The operating frequency is 66 MHz.

ASJC Scopus Sachgebiete

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Architecture and VLSI implementation of a RISC core for a monolithic video signal processor. / Herrmann, Klaus; Seifert, Martin; Gaedke, Klaus et al.
1994. 368-377 Beitrag in 1994 IEEE International Workshop VLSI Signal Processing, La Jolla, CA, USA.

Publikation: Konferenzbeitrag › Paper › Forschung › Peer-Review

Herrmann, K, Seifert, M, Gaedke, K, Jeschke, H & Pirsch, P 1994, 'Architecture and VLSI implementation of a RISC core for a monolithic video signal processor', Beitrag in 1994 IEEE International Workshop VLSI Signal Processing, La Jolla, CA, USA, 26 Okt. 1994 - 28 Okt. 1994 S. 368-377.
Herrmann, K., Seifert, M., Gaedke, K., Jeschke, H., & Pirsch, P. (1994). Architecture and VLSI implementation of a RISC core for a monolithic video signal processor. 368-377. Beitrag in 1994 IEEE International Workshop VLSI Signal Processing, La Jolla, CA, USA.
Herrmann K, Seifert M, Gaedke K, Jeschke H, Pirsch P. Architecture and VLSI implementation of a RISC core for a monolithic video signal processor. 1994. Beitrag in 1994 IEEE International Workshop VLSI Signal Processing, La Jolla, CA, USA.
Herrmann, Klaus ; Seifert, Martin ; Gaedke, Klaus et al. / Architecture and VLSI implementation of a RISC core for a monolithic video signal processor. Beitrag in 1994 IEEE International Workshop VLSI Signal Processing, La Jolla, CA, USA.10 S.
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@conference{f0249edeb53f49a882020fa670ac9a51,
title = "Architecture and VLSI implementation of a RISC core for a monolithic video signal processor",
abstract = "For a monolithic video signal processor a special RISC processor core has been developed. In order to achieve an efficient implementation of hybrid video coding algorithms the applied Harvard architecture with 16 bit data path is adapted to tasks like quantization, variable length coding and run length coding. The RISC processor's die size is 68.79 mm2 fabricated in a 0.8 μm CMOS technology. 4 kByte of program RAM and 512 Bytes of Data Memory are implemented on chip. The operating frequency is 66 MHz.",
author = "Klaus Herrmann and Martin Seifert and Klaus Gaedke and Hartwig Jeschke and Peter Pirsch",
year = "1994",
language = "English",
pages = "368--377",
note = "1994 IEEE International Workshop VLSI Signal Processing ; Conference date: 26-10-1994 Through 28-10-1994",

}

Download

TY - CONF

T1 - Architecture and VLSI implementation of a RISC core for a monolithic video signal processor

AU - Herrmann, Klaus

AU - Seifert, Martin

AU - Gaedke, Klaus

AU - Jeschke, Hartwig

AU - Pirsch, Peter

PY - 1994

Y1 - 1994

N2 - For a monolithic video signal processor a special RISC processor core has been developed. In order to achieve an efficient implementation of hybrid video coding algorithms the applied Harvard architecture with 16 bit data path is adapted to tasks like quantization, variable length coding and run length coding. The RISC processor's die size is 68.79 mm2 fabricated in a 0.8 μm CMOS technology. 4 kByte of program RAM and 512 Bytes of Data Memory are implemented on chip. The operating frequency is 66 MHz.

AB - For a monolithic video signal processor a special RISC processor core has been developed. In order to achieve an efficient implementation of hybrid video coding algorithms the applied Harvard architecture with 16 bit data path is adapted to tasks like quantization, variable length coding and run length coding. The RISC processor's die size is 68.79 mm2 fabricated in a 0.8 μm CMOS technology. 4 kByte of program RAM and 512 Bytes of Data Memory are implemented on chip. The operating frequency is 66 MHz.

UR - http://www.scopus.com/inward/record.url?scp=0028747398&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0028747398

SP - 368

EP - 377

T2 - 1994 IEEE International Workshop VLSI Signal Processing

Y2 - 26 October 1994 through 28 October 1994

ER -