Details
| Originalsprache | Englisch |
|---|---|
| Seiten (von - bis) | 609-612 |
| Seitenumfang | 4 |
| Fachzeitschrift | Proceedings - IEEE International Symposium on Circuits and Systems |
| Jahrgang | 1 |
| Publikationsstatus | Veröffentlicht - 1995 |
| Veranstaltung | The 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995. Part 3 (of 3) - Seattle, USA / Vereinigte Staaten Dauer: 30 Apr. 1995 → 3 Mai 1995 |
Abstract
The architecture of dedicated MPEG2 HDTV-decoders for stand-alone and hierarchical transmission has been investigated. The high demands on the video memory in terms of memory capacity and data rate are met by using synchronous DRAMs and adapting the data accesses to the properties of the memory devices. Thus compact implementations for consumer and professional decoders become possible.
ASJC Scopus Sachgebiete
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
Zitieren
- Standard
- Harvard
- Apa
- Vancouver
- BibTex
- RIS
in: Proceedings - IEEE International Symposium on Circuits and Systems, Jahrgang 1, 1995, S. 609-612.
Publikation: Beitrag in Fachzeitschrift › Konferenzaufsatz in Fachzeitschrift › Forschung › Peer-Review
}
TY - JOUR
T1 - Architecture and memory requirements for stand-alone and hierarchical MPEG2 HDTV-decoders with synchronous DRAMs
AU - Winzker, Marco
AU - Pirsch, Peter
AU - Reimers, Jochen
PY - 1995
Y1 - 1995
N2 - The architecture of dedicated MPEG2 HDTV-decoders for stand-alone and hierarchical transmission has been investigated. The high demands on the video memory in terms of memory capacity and data rate are met by using synchronous DRAMs and adapting the data accesses to the properties of the memory devices. Thus compact implementations for consumer and professional decoders become possible.
AB - The architecture of dedicated MPEG2 HDTV-decoders for stand-alone and hierarchical transmission has been investigated. The high demands on the video memory in terms of memory capacity and data rate are met by using synchronous DRAMs and adapting the data accesses to the properties of the memory devices. Thus compact implementations for consumer and professional decoders become possible.
UR - http://www.scopus.com/inward/record.url?scp=0029194177&partnerID=8YFLogxK
M3 - Conference article
AN - SCOPUS:0029194177
VL - 1
SP - 609
EP - 612
JO - Proceedings - IEEE International Symposium on Circuits and Systems
JF - Proceedings - IEEE International Symposium on Circuits and Systems
SN - 0271-4310
T2 - The 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995. Part 3 (of 3)
Y2 - 30 April 1995 through 3 May 1995
ER -