Details
Originalsprache | Englisch |
---|---|
Titel des Sammelwerks | ESSDERC 2006 |
Untertitel | Proceedings of the 36th European Solid-State Device Research Conference |
Herausgeber (Verlag) | IEEE Computer Society |
Seiten | 150-153 |
Seitenumfang | 4 |
ISBN (Print) | 1424403014, 9781424403011 |
Publikationsstatus | Veröffentlicht - 2006 |
Veranstaltung | ESSDERC 2006 - 36th European Solid-State Device Research Conference - Montreux, Schweiz Dauer: 19 Sept. 2006 → 21 Sept. 2006 |
Abstract
Two process concepts for Integration of novel gate stacks with epitaxial high-K dielectrics and metal gate electrodes are presented. A "gate first" process based on a planar gate stack on ultra thin SOI material has been used for successful fabrication of MOSFETs with TiN/Gd3O 3 gate stack. Furthermore MOSFETs with W/Gd2O3 gate stack have been fabricated with a replacement gate process. This is the first successful attempt to integrate crystalline high-K dielectrics into a "gentle" damascene metal gate process in order to reduce process induced oxide damages.
ASJC Scopus Sachgebiete
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
- Werkstoffwissenschaften (insg.)
- Elektronische, optische und magnetische Materialien
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ESSDERC 2006 : Proceedings of the 36th European Solid-State Device Research Conference. IEEE Computer Society, 2006. S. 150-153 4099878.
Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review
}
TY - GEN
T1 - Approaches to CMOS integration of epitaxial gadolinium oxide high-K dielectrics
AU - Gottlob, H. D.B.
AU - Echtermeyer, T.
AU - Mollenhauer, T.
AU - Schmidt, M.
AU - Efavi, J. K.
AU - Wahlbrink, T.
AU - Lemme, M. C.
AU - Kurz, H.
AU - Endres, R.
AU - Stefanov, Y.
AU - Schwalke, U.
AU - Czernohorsky, M.
AU - Bugiel, E.
AU - Fissel, A.
AU - Osten, H. J.
PY - 2006
Y1 - 2006
N2 - Two process concepts for Integration of novel gate stacks with epitaxial high-K dielectrics and metal gate electrodes are presented. A "gate first" process based on a planar gate stack on ultra thin SOI material has been used for successful fabrication of MOSFETs with TiN/Gd3O 3 gate stack. Furthermore MOSFETs with W/Gd2O3 gate stack have been fabricated with a replacement gate process. This is the first successful attempt to integrate crystalline high-K dielectrics into a "gentle" damascene metal gate process in order to reduce process induced oxide damages.
AB - Two process concepts for Integration of novel gate stacks with epitaxial high-K dielectrics and metal gate electrodes are presented. A "gate first" process based on a planar gate stack on ultra thin SOI material has been used for successful fabrication of MOSFETs with TiN/Gd3O 3 gate stack. Furthermore MOSFETs with W/Gd2O3 gate stack have been fabricated with a replacement gate process. This is the first successful attempt to integrate crystalline high-K dielectrics into a "gentle" damascene metal gate process in order to reduce process induced oxide damages.
UR - http://www.scopus.com/inward/record.url?scp=84943200196&partnerID=8YFLogxK
U2 - 10.1109/ESSDER.2006.307660
DO - 10.1109/ESSDER.2006.307660
M3 - Conference contribution
AN - SCOPUS:84943200196
SN - 1424403014
SN - 9781424403011
SP - 150
EP - 153
BT - ESSDERC 2006
PB - IEEE Computer Society
T2 - ESSDERC 2006 - 36th European Solid-State Device Research Conference
Y2 - 19 September 2006 through 21 September 2006
ER -