Details
| Originalsprache | Englisch |
|---|---|
| Seiten (von - bis) | 129-143 |
| Seitenumfang | 15 |
| Fachzeitschrift | Journal of Signal Processing Systems |
| Jahrgang | 53 |
| Ausgabenummer | 1 |
| Publikationsstatus | Veröffentlicht - 20 Mai 2008 |
| Extern publiziert | Ja |
Abstract
This paper presents a novel architecture combining an application specific instruction set processor (ASIP) core and an application domain specific embedded FPGAs (eFPGAs) used as flexible accelerator for the ASIP. The eFPGA is based on a parametrisable architecture template optimised for arithmetic oriented applications. It was designed as a physically optimised VLSI-macro using a flexible design methodology also sketched in this paper. Quantitative comparisons of the eFPGA with a commercial standard FPGA show significant improvements in energy, area and timing delays. Simulations of the new ASIP-eFPGA architecture have been conducted using a model based approach to evaluate its efficiency. The results show that power- and area-efficiencies similar to an FPGA can be achieved for the flexible ASIP-eFPGA while preserving the flexibility of a software programmable processor.
ASJC Scopus Sachgebiete
- Ingenieurwesen (insg.)
- Steuerungs- und Systemtechnik
- Mathematik (insg.)
- Theoretische Informatik
- Informatik (insg.)
- Signalverarbeitung
- Informatik (insg.)
- Information systems
- Mathematik (insg.)
- Modellierung und Simulation
- Informatik (insg.)
- Hardware und Architektur
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in: Journal of Signal Processing Systems, Jahrgang 53, Nr. 1, 20.05.2008, S. 129-143.
Publikation: Beitrag in Fachzeitschrift › Artikel › Forschung › Peer-Review
}
TY - JOUR
T1 - Application Domain Specific Embedded FPGAs for Flexible ISA-Extension of ASIPs
AU - Neumann, B.
AU - Von Sydow, T.
AU - Blume, H.
AU - Noll, T. G.
N1 - Funding information: This work is funded by the German Research Foundation (Deutsche Forschungsgemeinschaft, DFG) as part of the DFG Priority Program 1148 (Reconfigurable Computing Systems).
PY - 2008/5/20
Y1 - 2008/5/20
N2 - This paper presents a novel architecture combining an application specific instruction set processor (ASIP) core and an application domain specific embedded FPGAs (eFPGAs) used as flexible accelerator for the ASIP. The eFPGA is based on a parametrisable architecture template optimised for arithmetic oriented applications. It was designed as a physically optimised VLSI-macro using a flexible design methodology also sketched in this paper. Quantitative comparisons of the eFPGA with a commercial standard FPGA show significant improvements in energy, area and timing delays. Simulations of the new ASIP-eFPGA architecture have been conducted using a model based approach to evaluate its efficiency. The results show that power- and area-efficiencies similar to an FPGA can be achieved for the flexible ASIP-eFPGA while preserving the flexibility of a software programmable processor.
AB - This paper presents a novel architecture combining an application specific instruction set processor (ASIP) core and an application domain specific embedded FPGAs (eFPGAs) used as flexible accelerator for the ASIP. The eFPGA is based on a parametrisable architecture template optimised for arithmetic oriented applications. It was designed as a physically optimised VLSI-macro using a flexible design methodology also sketched in this paper. Quantitative comparisons of the eFPGA with a commercial standard FPGA show significant improvements in energy, area and timing delays. Simulations of the new ASIP-eFPGA architecture have been conducted using a model based approach to evaluate its efficiency. The results show that power- and area-efficiencies similar to an FPGA can be achieved for the flexible ASIP-eFPGA while preserving the flexibility of a software programmable processor.
KW - Arithmetic oriented
KW - ASIP
KW - EFPGA
KW - Parametrisable architecture
KW - Processor-eFPGA coupling
UR - http://www.scopus.com/inward/record.url?scp=54249096450&partnerID=8YFLogxK
U2 - 10.1007/s11265-008-0211-9
DO - 10.1007/s11265-008-0211-9
M3 - Article
AN - SCOPUS:54249096450
VL - 53
SP - 129
EP - 143
JO - Journal of Signal Processing Systems
JF - Journal of Signal Processing Systems
SN - 1939-8018
IS - 1
ER -