Details
| Originalsprache | Englisch |
|---|---|
| Seiten (von - bis) | 1745-1755 |
| Seitenumfang | 11 |
| Fachzeitschrift | IEEE Journal of Solid-State Circuits |
| Jahrgang | 36 |
| Ausgabenummer | 11 |
| Publikationsstatus | Veröffentlicht - Nov. 2001 |
| Extern publiziert | Ja |
Abstract
Current sensing in SRAMs is very promising to achieve high-speed operation in low-voltage applications. However, so far, a main limitation of the practical use of current sense amplifiers is the finite resistance of the bitline multiplexer (MUX). In this paper, the MUX itself and its influence on two types of current sense amplifiers is analyzed. It is shown that the MUX causes a significant performance degradation. A principle is presented to compensate for the bitline multiplexer by means of a current sense amplifier with improved feedback structure. The proposed solution is implemented in a 512 × 24 bit SRAM macro in 0.18-μm 1.8-V CMOS. It is shown by theory and measurements that, using the proposed circuit, it is possible to fully compensate for the MUX in terms of speed and signal amplitude with only little layout area penalty. A speed improvement due to the compensation of typically 0.5 ns is measured.
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- Elektrotechnik und Elektronik
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in: IEEE Journal of Solid-State Circuits, Jahrgang 36, Nr. 11, 11.2001, S. 1745-1755.
Publikation: Beitrag in Fachzeitschrift › Artikel › Forschung › Peer-Review
}
TY - JOUR
T1 - Analysis and compensation of the bitline multiplexer in SRAM current sense amplifiers
AU - Wicht, Bernhard
AU - Paul, Steffen
AU - Schmitt-Landsiedel, Doris
PY - 2001/11
Y1 - 2001/11
N2 - Current sensing in SRAMs is very promising to achieve high-speed operation in low-voltage applications. However, so far, a main limitation of the practical use of current sense amplifiers is the finite resistance of the bitline multiplexer (MUX). In this paper, the MUX itself and its influence on two types of current sense amplifiers is analyzed. It is shown that the MUX causes a significant performance degradation. A principle is presented to compensate for the bitline multiplexer by means of a current sense amplifier with improved feedback structure. The proposed solution is implemented in a 512 × 24 bit SRAM macro in 0.18-μm 1.8-V CMOS. It is shown by theory and measurements that, using the proposed circuit, it is possible to fully compensate for the MUX in terms of speed and signal amplitude with only little layout area penalty. A speed improvement due to the compensation of typically 0.5 ns is measured.
AB - Current sensing in SRAMs is very promising to achieve high-speed operation in low-voltage applications. However, so far, a main limitation of the practical use of current sense amplifiers is the finite resistance of the bitline multiplexer (MUX). In this paper, the MUX itself and its influence on two types of current sense amplifiers is analyzed. It is shown that the MUX causes a significant performance degradation. A principle is presented to compensate for the bitline multiplexer by means of a current sense amplifier with improved feedback structure. The proposed solution is implemented in a 512 × 24 bit SRAM macro in 0.18-μm 1.8-V CMOS. It is shown by theory and measurements that, using the proposed circuit, it is possible to fully compensate for the MUX in terms of speed and signal amplitude with only little layout area penalty. A speed improvement due to the compensation of typically 0.5 ns is measured.
KW - Bitline multiplexer
KW - Current sense amplifier
KW - Current sensing
KW - MOS transistor switch
KW - Multiplexer compensation
KW - Multiplexer resistance
KW - SRAM circuits
UR - http://www.scopus.com/inward/record.url?scp=0035505539&partnerID=8YFLogxK
U2 - 10.1109/4.962297
DO - 10.1109/4.962297
M3 - Article
AN - SCOPUS:0035505539
VL - 36
SP - 1745
EP - 1755
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 11
ER -