Details
| Originalsprache | Englisch |
|---|---|
| Titel des Sammelwerks | 1997 IEEE 1st Workshop on Multimedia Signal Processing, MMSP 1997 |
| Herausgeber/-innen | Yao Wang, Amy R. Reibman, B. H. Juang, Tsuhan Chen, Sun-Yuan Kung |
| Herausgeber (Verlag) | Institute of Electrical and Electronics Engineers Inc. |
| Seiten | 433-438 |
| Seitenumfang | 6 |
| ISBN (elektronisch) | 0780337808, 9780780337800 |
| Publikationsstatus | Veröffentlicht - 1997 |
| Veranstaltung | 1st IEEE Workshop on Multimedia Signal Processing, MMSP 1997 - Princeton, USA / Vereinigte Staaten Dauer: 23 Juni 1997 → 25 Juni 1997 |
Publikationsreihe
| Name | 1997 IEEE 1st Workshop on Multimedia Signal Processing, MMSP 1997 |
|---|
Abstract
A number of recently published DSPs and multimedia processors emphasize on Very Long Instruction Word (VLIW) architectures to achieve flexibility, processing power and high-level language programmability needed for future multimedia applications. In this paper we show that exclusive exploitation of instruction level parallelism decreases in efficiency as the degree of parallelism increases. This is mainly caused by algorithm characteristics, VLSI design and compiler restrictions. We discuss selected aspects from these fields and possible solutions to upcoming bottlenecks from a practical point of view.
ASJC Scopus Sachgebiete
- Informatik (insg.)
- Signalverarbeitung
- Ingenieurwesen (insg.)
- Medientechnik
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- Apa
- Vancouver
- BibTex
- RIS
1997 IEEE 1st Workshop on Multimedia Signal Processing, MMSP 1997. Hrsg. / Yao Wang; Amy R. Reibman; B. H. Juang; Tsuhan Chen; Sun-Yuan Kung. Institute of Electrical and Electronics Engineers Inc., 1997. S. 433-438 602673 (1997 IEEE 1st Workshop on Multimedia Signal Processing, MMSP 1997).
Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review
}
TY - GEN
T1 - An algorithm-hardware-system approach to VLIW multimedia processors
AU - Kneip, Johannes
AU - Berekovic, Mladen
AU - Pirsch, Peter
PY - 1997
Y1 - 1997
N2 - A number of recently published DSPs and multimedia processors emphasize on Very Long Instruction Word (VLIW) architectures to achieve flexibility, processing power and high-level language programmability needed for future multimedia applications. In this paper we show that exclusive exploitation of instruction level parallelism decreases in efficiency as the degree of parallelism increases. This is mainly caused by algorithm characteristics, VLSI design and compiler restrictions. We discuss selected aspects from these fields and possible solutions to upcoming bottlenecks from a practical point of view.
AB - A number of recently published DSPs and multimedia processors emphasize on Very Long Instruction Word (VLIW) architectures to achieve flexibility, processing power and high-level language programmability needed for future multimedia applications. In this paper we show that exclusive exploitation of instruction level parallelism decreases in efficiency as the degree of parallelism increases. This is mainly caused by algorithm characteristics, VLSI design and compiler restrictions. We discuss selected aspects from these fields and possible solutions to upcoming bottlenecks from a practical point of view.
UR - http://www.scopus.com/inward/record.url?scp=37249059665&partnerID=8YFLogxK
U2 - 10.1109/MMSP.1997.602673
DO - 10.1109/MMSP.1997.602673
M3 - Conference contribution
AN - SCOPUS:37249059665
T3 - 1997 IEEE 1st Workshop on Multimedia Signal Processing, MMSP 1997
SP - 433
EP - 438
BT - 1997 IEEE 1st Workshop on Multimedia Signal Processing, MMSP 1997
A2 - Wang, Yao
A2 - Reibman, Amy R.
A2 - Juang, B. H.
A2 - Chen, Tsuhan
A2 - Kung, Sun-Yuan
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 1st IEEE Workshop on Multimedia Signal Processing, MMSP 1997
Y2 - 23 June 1997 through 25 June 1997
ER -