Details
| Originalsprache | Englisch |
|---|---|
| Aufsatznummer | 7464806 |
| Seiten (von - bis) | 1705-1715 |
| Seitenumfang | 11 |
| Fachzeitschrift | IEEE Journal of Solid-State Circuits |
| Jahrgang | 51 |
| Ausgabenummer | 7 |
| Publikationsstatus | Veröffentlicht - Juli 2016 |
| Extern publiziert | Ja |
Abstract
A highly integrated synchronous buck converter with a predictive dead time control for input voltages > 18 V with 10 MHz switching frequency is presented. A high resolution dead time of ∼ 125 ps} allows to reduce dead time dependent losses without requiring body diode conduction to evaluate the dead time. High resolution is achieved by frequency compensated sampling of the switching node and by an 8 bit differential delay chain. Dead time parameters are derived in a comprehensive study of dead time depended losses. This way, the efficiency of fast switching DCDC converters can be optimized by eliminating the body diode forward conduction losses, minimizing reverse recovery losses and by achieving zero voltage switching. High-speed circuit blocks for fast switching operation are presented including level shifter, gate driver, PWM generator. The converter has been implemented in a 180 nm high-voltage BiCMOS technology. The power losses were measured to be reduced by up to 31% by the proposed dead time control, which results in a 5.3% efficiency increase at VIN = 18 V, VOUT = 5 V, and 0.45 A load. At VIN = 12 V, the peak efficiency is 81.2% with an efficiency improvement of 6% with dead time control.
ASJC Scopus Sachgebiete
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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in: IEEE Journal of Solid-State Circuits, Jahrgang 51, Nr. 7, 7464806, 07.2016, S. 1705-1715.
Publikation: Beitrag in Fachzeitschrift › Artikel › Forschung › Peer-Review
}
TY - JOUR
T1 - An 18 v Input 10 MHz Buck Converter with 125 ps Mixed-Signal Dead Time Control
AU - Wittmann, Juergen
AU - Barner, Alexander
AU - Rosahl, Thoralf
AU - Wicht, Bernhard
N1 - Publisher Copyright: © 2016 IEEE.
PY - 2016/7
Y1 - 2016/7
N2 - A highly integrated synchronous buck converter with a predictive dead time control for input voltages > 18 V with 10 MHz switching frequency is presented. A high resolution dead time of ∼ 125 ps} allows to reduce dead time dependent losses without requiring body diode conduction to evaluate the dead time. High resolution is achieved by frequency compensated sampling of the switching node and by an 8 bit differential delay chain. Dead time parameters are derived in a comprehensive study of dead time depended losses. This way, the efficiency of fast switching DCDC converters can be optimized by eliminating the body diode forward conduction losses, minimizing reverse recovery losses and by achieving zero voltage switching. High-speed circuit blocks for fast switching operation are presented including level shifter, gate driver, PWM generator. The converter has been implemented in a 180 nm high-voltage BiCMOS technology. The power losses were measured to be reduced by up to 31% by the proposed dead time control, which results in a 5.3% efficiency increase at VIN = 18 V, VOUT = 5 V, and 0.45 A load. At VIN = 12 V, the peak efficiency is 81.2% with an efficiency improvement of 6% with dead time control.
AB - A highly integrated synchronous buck converter with a predictive dead time control for input voltages > 18 V with 10 MHz switching frequency is presented. A high resolution dead time of ∼ 125 ps} allows to reduce dead time dependent losses without requiring body diode conduction to evaluate the dead time. High resolution is achieved by frequency compensated sampling of the switching node and by an 8 bit differential delay chain. Dead time parameters are derived in a comprehensive study of dead time depended losses. This way, the efficiency of fast switching DCDC converters can be optimized by eliminating the body diode forward conduction losses, minimizing reverse recovery losses and by achieving zero voltage switching. High-speed circuit blocks for fast switching operation are presented including level shifter, gate driver, PWM generator. The converter has been implemented in a 180 nm high-voltage BiCMOS technology. The power losses were measured to be reduced by up to 31% by the proposed dead time control, which results in a 5.3% efficiency increase at VIN = 18 V, VOUT = 5 V, and 0.45 A load. At VIN = 12 V, the peak efficiency is 81.2% with an efficiency improvement of 6% with dead time control.
KW - Buck converter
KW - mixed-signal
KW - multi-MHz
KW - predictive dead time control
KW - regulation
KW - sample and hold
KW - zerovoltage switching
UR - http://www.scopus.com/inward/record.url?scp=84966351241&partnerID=8YFLogxK
U2 - 10.1109/jssc.2016.2550498
DO - 10.1109/jssc.2016.2550498
M3 - Article
AN - SCOPUS:84966351241
VL - 51
SP - 1705
EP - 1715
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 7
M1 - 7464806
ER -