Details
| Originalsprache | Englisch |
|---|---|
| Seiten (von - bis) | 248-254 |
| Seitenumfang | 7 |
| Fachzeitschrift | Proceedings of SPIE - The International Society for Optical Engineering |
| Jahrgang | 3526 |
| Publikationsstatus | Veröffentlicht - 8 Okt. 1998 |
| Veranstaltung | Configuralble Computing: Technology and Applications - Boston, MA, USA / Vereinigte Staaten Dauer: 2 Nov. 1998 → 3 Nov. 1998 |
Abstract
Finite impulse response filters (FIR filters) are very commonly used in digital signal processing (DSP) applications and are traditionally implemented using ASICs or DSP-processors. For FPGA implementation, due to the high throughput rate and large computational power required under real-time constraints, they are a challenging subject. Indeed, the limitation of resources on FPGA, i.e., logic blocks and flip flops, and furthermore, the high routing delays, requires compact implementations of the circuits. Three approaches for implementation of high-performance symmetric FIR filters on lookup table-based FPGAs will be considered in this paper: Fully parallel distributed arithmetic, table lookup multiplication, and conventional hardware multiplication. Implementation results will be illustrated by an 8 taps 8 bits symmetric FIR filter, and comparative considerations of the above approaches invoked for Xilinx FPGAs will be also shown.
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- Werkstoffwissenschaften (insg.)
- Elektronische, optische und magnetische Materialien
- Physik und Astronomie (insg.)
- Physik der kondensierten Materie
- Informatik (insg.)
- Angewandte Informatik
- Mathematik (insg.)
- Angewandte Mathematik
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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in: Proceedings of SPIE - The International Society for Optical Engineering, Jahrgang 3526, 08.10.1998, S. 248-254.
Publikation: Beitrag in Fachzeitschrift › Konferenzaufsatz in Fachzeitschrift › Forschung › Peer-Review
}
TY - JOUR
T1 - Alternative approaches implementing high-performance FIR filters on lookup table-based FPGAs
T2 - Configuralble Computing: Technology and Applications
AU - Do, Tien Toan
AU - Kropp, Holger
AU - Reuter, Carsten
AU - Pirsch, Peter
PY - 1998/10/8
Y1 - 1998/10/8
N2 - Finite impulse response filters (FIR filters) are very commonly used in digital signal processing (DSP) applications and are traditionally implemented using ASICs or DSP-processors. For FPGA implementation, due to the high throughput rate and large computational power required under real-time constraints, they are a challenging subject. Indeed, the limitation of resources on FPGA, i.e., logic blocks and flip flops, and furthermore, the high routing delays, requires compact implementations of the circuits. Three approaches for implementation of high-performance symmetric FIR filters on lookup table-based FPGAs will be considered in this paper: Fully parallel distributed arithmetic, table lookup multiplication, and conventional hardware multiplication. Implementation results will be illustrated by an 8 taps 8 bits symmetric FIR filter, and comparative considerations of the above approaches invoked for Xilinx FPGAs will be also shown.
AB - Finite impulse response filters (FIR filters) are very commonly used in digital signal processing (DSP) applications and are traditionally implemented using ASICs or DSP-processors. For FPGA implementation, due to the high throughput rate and large computational power required under real-time constraints, they are a challenging subject. Indeed, the limitation of resources on FPGA, i.e., logic blocks and flip flops, and furthermore, the high routing delays, requires compact implementations of the circuits. Three approaches for implementation of high-performance symmetric FIR filters on lookup table-based FPGAs will be considered in this paper: Fully parallel distributed arithmetic, table lookup multiplication, and conventional hardware multiplication. Implementation results will be illustrated by an 8 taps 8 bits symmetric FIR filter, and comparative considerations of the above approaches invoked for Xilinx FPGAs will be also shown.
KW - Hardware emulation
KW - High-performance FIR-filters
KW - Lookup table-based FPGAs
KW - Multiply-intensive algorithms
UR - http://www.scopus.com/inward/record.url?scp=0037960230&partnerID=8YFLogxK
U2 - 10.1117/12.327043
DO - 10.1117/12.327043
M3 - Conference article
AN - SCOPUS:0037960230
VL - 3526
SP - 248
EP - 254
JO - Proceedings of SPIE - The International Society for Optical Engineering
JF - Proceedings of SPIE - The International Society for Optical Engineering
SN - 0277-786X
Y2 - 2 November 1998 through 3 November 1998
ER -