Details
| Originalsprache | Englisch |
|---|---|
| Seiten (von - bis) | 781-791 |
| Seitenumfang | 11 |
| Fachzeitschrift | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Jahrgang | 16 |
| Ausgabenummer | 7 |
| Publikationsstatus | Veröffentlicht - Juli 2008 |
| Extern publiziert | Ja |
Abstract
A novel implementation of a tag sorting circuit for a weighted fair queueing (WFQ) enabled Internet Protocol (IP) packet scheduler is presented. The design consists of a search tree, matching circuitry, and a custom memory layout. It is implemented using 130-nm silicon technology and supports quality of service (QoS) on networks at line speeds of 40 Gb/s, enabling next generation IP services to be deployed.
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in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Jahrgang 16, Nr. 7, 07.2008, S. 781-791.
Publikation: Beitrag in Fachzeitschrift › Artikel › Forschung › Peer-Review
}
TY - JOUR
T1 - A Scalable Packet Sorting Circuit for High-Speed WFQ Packet Scheduling
AU - McLaughlin, K.
AU - Sezer, S.
AU - Blume, H.
AU - Yang, X.
AU - Kupzog, F.
AU - Noll, T.
N1 - Funding information: Manuscript received April 1, 2007; revised July 3, 2007. This work was supported by Invest Northern Ireland and the Department for Employment and Learning. It is protected by Patent No. 0524845.
PY - 2008/7
Y1 - 2008/7
N2 - A novel implementation of a tag sorting circuit for a weighted fair queueing (WFQ) enabled Internet Protocol (IP) packet scheduler is presented. The design consists of a search tree, matching circuitry, and a custom memory layout. It is implemented using 130-nm silicon technology and supports quality of service (QoS) on networks at line speeds of 40 Gb/s, enabling next generation IP services to be deployed.
AB - A novel implementation of a tag sorting circuit for a weighted fair queueing (WFQ) enabled Internet Protocol (IP) packet scheduler is presented. The design consists of a search tree, matching circuitry, and a custom memory layout. It is implemented using 130-nm silicon technology and supports quality of service (QoS) on networks at line speeds of 40 Gb/s, enabling next generation IP services to be deployed.
KW - Internet packet scheduling
KW - Lookup, quality of service (QoS)
KW - Time-stamp sorting
KW - Traffic management
KW - Weighted fair queueing (WFQ)
UR - http://www.scopus.com/inward/record.url?scp=48149099928&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2008.2000323
DO - 10.1109/TVLSI.2008.2000323
M3 - Article
AN - SCOPUS:48149099928
VL - 16
SP - 781
EP - 791
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 7
ER -