Details
| Originalsprache | Englisch |
|---|---|
| Titel des Sammelwerks | 2020 9th International Conference on Modern Circuits and Systems Technologies (MOCAST) |
| Seiten | 1-6 |
| Seitenumfang | 6 |
| ISBN (elektronisch) | 9781728166872 |
| Publikationsstatus | Veröffentlicht - 2020 |
Abstract
In this paper, an operand masking approach is proposed to achieve lower energy consumption using approximate computing techniques in programmable high-performance processors, in this case horizontal and vertical SIMD vector processors for embedded computer vision applications. Contrary to state-of-the-art dedicated approximate arithmetic circuits, this mechanism enables programmable fine-grained accuracy control and switching energy reduction at runtime. An evaluation for a 45 nm ASIC technology shows a total effective energy reduction of up to 4.5% for a horizontal SIMD vector processor architecture executing approximate SIFT image feature extraction for an error-resilient egomotion estimation algorithm.
ASJC Scopus Sachgebiete
- Informatik (insg.)
- Computernetzwerke und -kommunikation
- Informatik (insg.)
- Hardware und Architektur
- Energie (insg.)
- Energieanlagenbau und Kraftwerkstechnik
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
- Ingenieurwesen (insg.)
- Sicherheit, Risiko, Zuverlässigkeit und Qualität
- Mathematik (insg.)
- Steuerung und Optimierung
Ziele für nachhaltige Entwicklung
Zitieren
- Standard
- Harvard
- Apa
- Vancouver
- BibTex
- RIS
2020 9th International Conference on Modern Circuits and Systems Technologies (MOCAST). 2020. S. 1-6 9200278.
Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review
}
TY - GEN
T1 - A Runtime-Reconfigurable Operand Masking Technique for Energy-Efficient Approximate Processor Architectures
AU - Weißbrich, M.
AU - García-Ortiz, A.
AU - Payá-Vayá, G.
N1 - Funding information: This work was partly funded by the German Research Council (DFG) under project number PA 2762/1-1.
PY - 2020
Y1 - 2020
N2 - In this paper, an operand masking approach is proposed to achieve lower energy consumption using approximate computing techniques in programmable high-performance processors, in this case horizontal and vertical SIMD vector processors for embedded computer vision applications. Contrary to state-of-the-art dedicated approximate arithmetic circuits, this mechanism enables programmable fine-grained accuracy control and switching energy reduction at runtime. An evaluation for a 45 nm ASIC technology shows a total effective energy reduction of up to 4.5% for a horizontal SIMD vector processor architecture executing approximate SIFT image feature extraction for an error-resilient egomotion estimation algorithm.
AB - In this paper, an operand masking approach is proposed to achieve lower energy consumption using approximate computing techniques in programmable high-performance processors, in this case horizontal and vertical SIMD vector processors for embedded computer vision applications. Contrary to state-of-the-art dedicated approximate arithmetic circuits, this mechanism enables programmable fine-grained accuracy control and switching energy reduction at runtime. An evaluation for a 45 nm ASIC technology shows a total effective energy reduction of up to 4.5% for a horizontal SIMD vector processor architecture executing approximate SIFT image feature extraction for an error-resilient egomotion estimation algorithm.
KW - Approximate Computing
KW - Energy Efficiency
KW - Error-Resilient Applications
KW - Feature Extraction
KW - Processor Architectures
UR - http://www.scopus.com/inward/record.url?scp=85093862136&partnerID=8YFLogxK
U2 - 10.1109/mocast49295.2020.9200278
DO - 10.1109/mocast49295.2020.9200278
M3 - Conference contribution
SN - 978-1-7281-6688-9
SP - 1
EP - 6
BT - 2020 9th International Conference on Modern Circuits and Systems Technologies (MOCAST)
ER -