Details
Originalsprache | Englisch |
---|---|
Titel des Sammelwerks | Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 |
Herausgeber/-innen | John Chickanosky, Ram K. Krishnamurthy, P.R. Mukund |
Herausgeber (Verlag) | Institute of Electrical and Electronics Engineers Inc. |
Seiten | 416-420 |
Seitenumfang | 5 |
ISBN (elektronisch) | 0780374940 |
Publikationsstatus | Veröffentlicht - 2002 |
Veranstaltung | 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 - Rochester, USA / Vereinigte Staaten Dauer: 25 Sept. 2002 → 28 Sept. 2002 |
Publikationsreihe
Name | Proceedings of the Annual IEEE International ASIC Conference and Exhibit |
---|---|
Band | 2002-January |
ISSN (Print) | 1063-0988 |
Abstract
We propose a new force-directed placement method for a cell based interconnect centric design flow. While the standard implementation of force-directed placement uses one attracting and one repelling force, we add a third force to each cell. This additional force represents the timing constraints of the design. For each path a cell belongs to, a force is applied to this cell to influence the length of the path. These forces depend on the timing constraints of the paths and are calculated together with the repelling forces. The force applied to every cell can be attracting, if the path constraint is not fulfilled or repelling, if the constraint is surpassed. First experimental results show that in comparison with a standard implementation of a force-directed placer the path length of critical paths is shorter.
ASJC Scopus Sachgebiete
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
Zitieren
- Standard
- Harvard
- Apa
- Vancouver
- BibTex
- RIS
Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002. Hrsg. / John Chickanosky; Ram K. Krishnamurthy; P.R. Mukund. Institute of Electrical and Electronics Engineers Inc., 2002. S. 416-420 1158095 (Proceedings of the Annual IEEE International ASIC Conference and Exhibit; Band 2002-January).
Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review
}
TY - GEN
T1 - A new placement algorithm for an interconnect centric design flow
AU - Malonnek, C.
AU - Olbrich, M.
AU - Barke, E.
N1 - Publisher Copyright: © 2002 IEEE.
PY - 2002
Y1 - 2002
N2 - We propose a new force-directed placement method for a cell based interconnect centric design flow. While the standard implementation of force-directed placement uses one attracting and one repelling force, we add a third force to each cell. This additional force represents the timing constraints of the design. For each path a cell belongs to, a force is applied to this cell to influence the length of the path. These forces depend on the timing constraints of the paths and are calculated together with the repelling forces. The force applied to every cell can be attracting, if the path constraint is not fulfilled or repelling, if the constraint is surpassed. First experimental results show that in comparison with a standard implementation of a force-directed placer the path length of critical paths is shorter.
AB - We propose a new force-directed placement method for a cell based interconnect centric design flow. While the standard implementation of force-directed placement uses one attracting and one repelling force, we add a third force to each cell. This additional force represents the timing constraints of the design. For each path a cell belongs to, a force is applied to this cell to influence the length of the path. These forces depend on the timing constraints of the paths and are calculated together with the repelling forces. The force applied to every cell can be attracting, if the path constraint is not fulfilled or repelling, if the constraint is surpassed. First experimental results show that in comparison with a standard implementation of a force-directed placer the path length of critical paths is shorter.
UR - http://www.scopus.com/inward/record.url?scp=33745804719&partnerID=8YFLogxK
U2 - 10.1109/ASIC.2002.1158095
DO - 10.1109/ASIC.2002.1158095
M3 - Conference contribution
AN - SCOPUS:33745804719
T3 - Proceedings of the Annual IEEE International ASIC Conference and Exhibit
SP - 416
EP - 420
BT - Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
A2 - Chickanosky, John
A2 - Krishnamurthy, Ram K.
A2 - Mukund, P.R.
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
Y2 - 25 September 2002 through 28 September 2002
ER -