Details
| Originalsprache | Englisch |
|---|---|
| Seiten (von - bis) | 131-141 |
| Seitenumfang | 11 |
| Fachzeitschrift | Proceedings of SPIE - The International Society for Optical Engineering |
| Jahrgang | 3311 |
| Publikationsstatus | Veröffentlicht - 26 März 1998 |
| Veranstaltung | Multimedia Hardware Architectures 1998 - San Jose, CA, USA / Vereinigte Staaten Dauer: 29 Jan. 1998 → 30 Jan. 1998 |
Abstract
Demand for highly flexible and fast implementations for bitstream parsing and variable-length-decoding (VLD) arises, if applications are targeted that shall support either MPEG-4 or multiple standards like MPEG-2, H.263 or Dolby AC3. The paper shows that especially today's multimedia oriented RISC processors incorporating multiple parallel arithmetic units are slowed down by these kind of bit-level operations. Therefore, a new architecture is proposed, that adds function specific blocks into the data path of a RISC processor, that are highly adapted to the processing of variable-length coded bitstream data. The increased functional complexity of basic instructions results in a significant speedup over software implementations on standard RISC processors. Two typical functions, that are frequently used in bitstream parsing, ShowBits (reading a certain number of bits) and GetBits (reading and removing a certain number of bits from the incoming bitstream), are executed in a single clock-cycle with a 64 bit rotator circuit. Constant input-rate VLD of one, two or four bits per clock-cycle can be implemented using internal RAM. Lookup-tables can be used for word-parallel decoding and VLC. Optionally memory entries can be saved using content addressable memories (CAMs) in addition to a data RAM. The proposed architecture has been implemented as a functional extension to an existing RISC core with additional 9k gates of logic, 8k RAM and an interface to a CAM. Synthesis results show an estimate of 160 MHz achievable clock frequency using a 0.35 μ technology. The resulting performance is sufficient for MPEG-2 HDTV or MPEG-4 applications.
ASJC Scopus Sachgebiete
- Werkstoffwissenschaften (insg.)
- Elektronische, optische und magnetische Materialien
- Physik und Astronomie (insg.)
- Physik der kondensierten Materie
- Informatik (insg.)
- Angewandte Informatik
- Mathematik (insg.)
- Angewandte Mathematik
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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in: Proceedings of SPIE - The International Society for Optical Engineering, Jahrgang 3311, 26.03.1998, S. 131-141.
Publikation: Beitrag in Fachzeitschrift › Konferenzaufsatz in Fachzeitschrift › Forschung › Peer-Review
}
TY - JOUR
T1 - A multimedia RISC core for efficient bitstream parsing and VLD
AU - Berekovic, Mladen
AU - Meyer, Gerald
AU - Guo, Yong
AU - Pirsch, Peter
PY - 1998/3/26
Y1 - 1998/3/26
N2 - Demand for highly flexible and fast implementations for bitstream parsing and variable-length-decoding (VLD) arises, if applications are targeted that shall support either MPEG-4 or multiple standards like MPEG-2, H.263 or Dolby AC3. The paper shows that especially today's multimedia oriented RISC processors incorporating multiple parallel arithmetic units are slowed down by these kind of bit-level operations. Therefore, a new architecture is proposed, that adds function specific blocks into the data path of a RISC processor, that are highly adapted to the processing of variable-length coded bitstream data. The increased functional complexity of basic instructions results in a significant speedup over software implementations on standard RISC processors. Two typical functions, that are frequently used in bitstream parsing, ShowBits (reading a certain number of bits) and GetBits (reading and removing a certain number of bits from the incoming bitstream), are executed in a single clock-cycle with a 64 bit rotator circuit. Constant input-rate VLD of one, two or four bits per clock-cycle can be implemented using internal RAM. Lookup-tables can be used for word-parallel decoding and VLC. Optionally memory entries can be saved using content addressable memories (CAMs) in addition to a data RAM. The proposed architecture has been implemented as a functional extension to an existing RISC core with additional 9k gates of logic, 8k RAM and an interface to a CAM. Synthesis results show an estimate of 160 MHz achievable clock frequency using a 0.35 μ technology. The resulting performance is sufficient for MPEG-2 HDTV or MPEG-4 applications.
AB - Demand for highly flexible and fast implementations for bitstream parsing and variable-length-decoding (VLD) arises, if applications are targeted that shall support either MPEG-4 or multiple standards like MPEG-2, H.263 or Dolby AC3. The paper shows that especially today's multimedia oriented RISC processors incorporating multiple parallel arithmetic units are slowed down by these kind of bit-level operations. Therefore, a new architecture is proposed, that adds function specific blocks into the data path of a RISC processor, that are highly adapted to the processing of variable-length coded bitstream data. The increased functional complexity of basic instructions results in a significant speedup over software implementations on standard RISC processors. Two typical functions, that are frequently used in bitstream parsing, ShowBits (reading a certain number of bits) and GetBits (reading and removing a certain number of bits from the incoming bitstream), are executed in a single clock-cycle with a 64 bit rotator circuit. Constant input-rate VLD of one, two or four bits per clock-cycle can be implemented using internal RAM. Lookup-tables can be used for word-parallel decoding and VLC. Optionally memory entries can be saved using content addressable memories (CAMs) in addition to a data RAM. The proposed architecture has been implemented as a functional extension to an existing RISC core with additional 9k gates of logic, 8k RAM and an interface to a CAM. Synthesis results show an estimate of 160 MHz achievable clock frequency using a 0.35 μ technology. The resulting performance is sufficient for MPEG-2 HDTV or MPEG-4 applications.
KW - Bitstream parsing
KW - Core
KW - Huffman Codes
KW - MPEG-4
KW - Programmable
KW - Reversible codes
KW - RISC
KW - VLC
KW - VLD
UR - http://www.scopus.com/inward/record.url?scp=0032400665&partnerID=8YFLogxK
U2 - 10.1117/12.304665
DO - 10.1117/12.304665
M3 - Conference article
AN - SCOPUS:0032400665
VL - 3311
SP - 131
EP - 141
JO - Proceedings of SPIE - The International Society for Optical Engineering
JF - Proceedings of SPIE - The International Society for Optical Engineering
SN - 0277-786X
T2 - Multimedia Hardware Architectures 1998
Y2 - 29 January 1998 through 30 January 1998
ER -