Details
| Originalsprache | Englisch |
|---|---|
| Titel des Sammelwerks | 2005 IEEE ICASSP '05 - Proc. |
| Untertitel | Design and Implementation of Signal Proces.Syst.,Indust. Technol. Track,Machine Learning for Signal Proces. Education, Spec. Sessions |
| Herausgeber (Verlag) | Institute of Electrical and Electronics Engineers Inc. |
| Seiten | V665-V668 |
| ISBN (Print) | 0780388747, 9780780388741 |
| Publikationsstatus | Veröffentlicht - 2005 |
| Veranstaltung | 2005 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '05 - Philadelphia, PA, USA / Vereinigte Staaten Dauer: 18 März 2005 → 23 März 2005 |
Publikationsreihe
| Name | ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings |
|---|---|
| Band | V |
| ISSN (Print) | 1520-6149 |
Abstract
A flexible SoC architecture and its hardware implementation targeting advanced MPEG-4 video coding and region-of-interest detection (ROI) is presented. The multi-core architecture integrates three fully programmable processors cores and various interfaces onto a single chip, all tied to a 64-Bit AMBA AHB bus. The processor cores are individually optimized to different computational characteristics, complementing each other to deliver high performance levels with high flexibility at reduced system cost. The SoC is fabricated in a 0.18 μm 6LM standard-cell technology, occupies about 82 mm2, and operates at 145 MHz. A surveillance application example includes a MPEG-4 Simple Profile encoder with preceding ROI detection for superior compression results in full TV resolution.
ASJC Scopus Sachgebiete
- Informatik (insg.)
- Software
- Informatik (insg.)
- Signalverarbeitung
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
Zitieren
- Standard
- Harvard
- Apa
- Vancouver
- BibTex
- RIS
2005 IEEE ICASSP '05 - Proc. : Design and Implementation of Signal Proces.Syst.,Indust. Technol. Track,Machine Learning for Signal Proces. Education, Spec. Sessions. Institute of Electrical and Electronics Engineers Inc., 2005. S. V665-V668 1416391 (ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings; Band V).
Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review
}
TY - GEN
T1 - A multi-core SoC design for advanced image and video compression
AU - Dehnhardt, A.
AU - Kulaczewski, M. B.
AU - Friebe, L.
AU - Moch, S.
AU - Pirsch, P.
AU - Stolberg, H. J.
AU - Reuter, C.
PY - 2005
Y1 - 2005
N2 - A flexible SoC architecture and its hardware implementation targeting advanced MPEG-4 video coding and region-of-interest detection (ROI) is presented. The multi-core architecture integrates three fully programmable processors cores and various interfaces onto a single chip, all tied to a 64-Bit AMBA AHB bus. The processor cores are individually optimized to different computational characteristics, complementing each other to deliver high performance levels with high flexibility at reduced system cost. The SoC is fabricated in a 0.18 μm 6LM standard-cell technology, occupies about 82 mm2, and operates at 145 MHz. A surveillance application example includes a MPEG-4 Simple Profile encoder with preceding ROI detection for superior compression results in full TV resolution.
AB - A flexible SoC architecture and its hardware implementation targeting advanced MPEG-4 video coding and region-of-interest detection (ROI) is presented. The multi-core architecture integrates three fully programmable processors cores and various interfaces onto a single chip, all tied to a 64-Bit AMBA AHB bus. The processor cores are individually optimized to different computational characteristics, complementing each other to deliver high performance levels with high flexibility at reduced system cost. The SoC is fabricated in a 0.18 μm 6LM standard-cell technology, occupies about 82 mm2, and operates at 145 MHz. A surveillance application example includes a MPEG-4 Simple Profile encoder with preceding ROI detection for superior compression results in full TV resolution.
UR - http://www.scopus.com/inward/record.url?scp=33646759959&partnerID=8YFLogxK
U2 - 10.1109/ICASSP.2005.1416391
DO - 10.1109/ICASSP.2005.1416391
M3 - Conference contribution
AN - SCOPUS:33646759959
SN - 0780388747
SN - 9780780388741
T3 - ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings
SP - V665-V668
BT - 2005 IEEE ICASSP '05 - Proc.
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2005 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP '05
Y2 - 18 March 2005 through 23 March 2005
ER -