Details
| Originalsprache | Englisch |
|---|---|
| Seiten (von - bis) | 1856-1868 |
| Seitenumfang | 13 |
| Fachzeitschrift | IEEE J. Solid State Circuits |
| Jahrgang | 53 |
| Ausgabenummer | 6 |
| Publikationsstatus | Veröffentlicht - Juni 2018 |
Abstract
This paper presents a dc-dc converter for integration in the power management unit of an ultra-low power microcontroller. The converter is designed to significantly reduce the wake-up energy and startup delay of the supplied core. The use of a minimized output capacitor is the key factor to save the wake-up energy. The converter is buffered with only 56 nF and guarantees a stable output of 1.2 V with a voltage ripple smaller than 30 mV. The controller of the proposed dc-dc converter is based on a predictive peak current control that allows the system to control the energy transfer at extremely low power consumption. The proposed circuit is implemented in 130-nm CMOS technology with an area of only 0.14 mm 2. It achieves a high conversion efficiency of 92.1% and a small quiescent current of 440 nA. It operates from 1.8 to 3.3 V with a maximum load of 2.65 mA.
ASJC Scopus Sachgebiete
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
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in: IEEE J. Solid State Circuits, Jahrgang 53, Nr. 6, 06.2018, S. 1856-1868.
Publikation: Beitrag in Fachzeitschrift › Artikel › Forschung › Peer-Review
}
TY - JOUR
T1 - A Hysteretic Buck Converter With 92.1% Maximum Efficiency Designed for Ultra-Low Power and Fast Wake-Up SoC Applications
AU - Santoro, Francesco
AU - Kuhn, Rüdiger
AU - Gibson, Neil
AU - Rasera, Nicola
AU - Tost, Thomas
AU - Graeb, Helmut
AU - Wicht, Bernhard
AU - Brederlow, Ralf
N1 - Publisher Copyright: © 1966-2012 IEEE.
PY - 2018/6
Y1 - 2018/6
N2 - This paper presents a dc-dc converter for integration in the power management unit of an ultra-low power microcontroller. The converter is designed to significantly reduce the wake-up energy and startup delay of the supplied core. The use of a minimized output capacitor is the key factor to save the wake-up energy. The converter is buffered with only 56 nF and guarantees a stable output of 1.2 V with a voltage ripple smaller than 30 mV. The controller of the proposed dc-dc converter is based on a predictive peak current control that allows the system to control the energy transfer at extremely low power consumption. The proposed circuit is implemented in 130-nm CMOS technology with an area of only 0.14 mm 2. It achieves a high conversion efficiency of 92.1% and a small quiescent current of 440 nA. It operates from 1.8 to 3.3 V with a maximum load of 2.65 mA.
AB - This paper presents a dc-dc converter for integration in the power management unit of an ultra-low power microcontroller. The converter is designed to significantly reduce the wake-up energy and startup delay of the supplied core. The use of a minimized output capacitor is the key factor to save the wake-up energy. The converter is buffered with only 56 nF and guarantees a stable output of 1.2 V with a voltage ripple smaller than 30 mV. The controller of the proposed dc-dc converter is based on a predictive peak current control that allows the system to control the energy transfer at extremely low power consumption. The proposed circuit is implemented in 130-nm CMOS technology with an area of only 0.14 mm 2. It achieves a high conversion efficiency of 92.1% and a small quiescent current of 440 nA. It operates from 1.8 to 3.3 V with a maximum load of 2.65 mA.
KW - Buck
KW - DC-DC
KW - fast wake-up
KW - low energy
KW - low power
KW - minimized capacitor
KW - wake-up energy
UR - http://www.scopus.com/inward/record.url?scp=85042199714&partnerID=8YFLogxK
U2 - 10.1109/jssc.2018.2799964
DO - 10.1109/jssc.2018.2799964
M3 - Article
VL - 53
SP - 1856
EP - 1868
JO - IEEE J. Solid State Circuits
JF - IEEE J. Solid State Circuits
SN - 1558-173X
IS - 6
ER -