Details
| Originalsprache | Englisch |
|---|---|
| Titel des Sammelwerks | Proceedings - 2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2024 |
| Herausgeber (Verlag) | Institute of Electrical and Electronics Engineers Inc. |
| ISBN (elektronisch) | 9798350351927 |
| Publikationsstatus | Veröffentlicht - 2024 |
| Veranstaltung | 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2024 - Volos, Griechenland Dauer: 2 Juli 2024 → 5 Juli 2024 |
Publikationsreihe
| Name | Proceedings - 2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2024 |
|---|
Abstract
This paper presents a digital topology for linearizing multi-bit feedback digital-to-analog converters (DACs) in delta-sigma modulators (Δ Σ Ms). The proposed topology significantly surpasses existing techniques in hardware utilization, efficiency, and implementation effort by simplifying the complex digital transfer functions in the digital linearization system to a gain-only transfer function and by sparing an explicit adder for the mismatch correction. These simplifications still allow an almost ideal linearization of the overall system, improving our exemplary Δ Σ M by more than 30dB in spurious free dynamic range (SFDR) as well as 33dB in signal to noise and distortion ratio (SNDR). Furthermore, the technique's hardware utilization is reduced by almost 50% compared to techniques utilizing complex transfer functions for the digital linearization. The presented linearization topology offers a practical and efficient solution for high-bandwidth systems reducing the implementation effort as well as the power consumption.
ASJC Scopus Sachgebiete
- Informatik (insg.)
- Hardware und Architektur
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
- Ingenieurwesen (insg.)
- Sicherheit, Risiko, Zuverlässigkeit und Qualität
- Mathematik (insg.)
- Modellierung und Simulation
- Physik und Astronomie (insg.)
- Instrumentierung
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Proceedings - 2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2024. Institute of Electrical and Electronics Engineers Inc., 2024. (Proceedings - 2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2024).
Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review
}
TY - GEN
T1 - A Hardware Efficient Digital DAC Linearization Topology for Delta-Sigma ADCs
AU - Flemming, Jesko
AU - Rogge, Timon
AU - Wicht, Bernhard
AU - Witte, Pascal
N1 - Publisher Copyright: © 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - This paper presents a digital topology for linearizing multi-bit feedback digital-to-analog converters (DACs) in delta-sigma modulators (Δ Σ Ms). The proposed topology significantly surpasses existing techniques in hardware utilization, efficiency, and implementation effort by simplifying the complex digital transfer functions in the digital linearization system to a gain-only transfer function and by sparing an explicit adder for the mismatch correction. These simplifications still allow an almost ideal linearization of the overall system, improving our exemplary Δ Σ M by more than 30dB in spurious free dynamic range (SFDR) as well as 33dB in signal to noise and distortion ratio (SNDR). Furthermore, the technique's hardware utilization is reduced by almost 50% compared to techniques utilizing complex transfer functions for the digital linearization. The presented linearization topology offers a practical and efficient solution for high-bandwidth systems reducing the implementation effort as well as the power consumption.
AB - This paper presents a digital topology for linearizing multi-bit feedback digital-to-analog converters (DACs) in delta-sigma modulators (Δ Σ Ms). The proposed topology significantly surpasses existing techniques in hardware utilization, efficiency, and implementation effort by simplifying the complex digital transfer functions in the digital linearization system to a gain-only transfer function and by sparing an explicit adder for the mismatch correction. These simplifications still allow an almost ideal linearization of the overall system, improving our exemplary Δ Σ M by more than 30dB in spurious free dynamic range (SFDR) as well as 33dB in signal to noise and distortion ratio (SNDR). Furthermore, the technique's hardware utilization is reduced by almost 50% compared to techniques utilizing complex transfer functions for the digital linearization. The presented linearization topology offers a practical and efficient solution for high-bandwidth systems reducing the implementation effort as well as the power consumption.
KW - analog-to-digital converter
KW - delta-sigma modulator
KW - efficient
KW - linearization
UR - http://www.scopus.com/inward/record.url?scp=85211899115&partnerID=8YFLogxK
U2 - 10.1109/SMACD61181.2024.10745378
DO - 10.1109/SMACD61181.2024.10745378
M3 - Conference contribution
AN - SCOPUS:85211899115
T3 - Proceedings - 2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2024
BT - Proceedings - 2024 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2024
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 20th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design, SMACD 2024
Y2 - 2 July 2024 through 5 July 2024
ER -