Details
| Originalsprache | Englisch |
|---|---|
| Titel des Sammelwerks | Field-Programmable Logic and Applications |
| Untertitel | From FPGAs to Computing Paradigm - 8th International Workshop, FPL 1998, Proceedings |
| Herausgeber/-innen | Reiner W. Hartenstein, Andres Keevallik |
| Herausgeber (Verlag) | Springer Verlag |
| Seiten | 441-445 |
| Seitenumfang | 5 |
| ISBN (Print) | 3540649484, 9783540649489 |
| Publikationsstatus | Veröffentlicht - 27 Mai 2006 |
| Veranstaltung | 8th International Workshop on Field-Programmable Logic and Applications, FPL 1998 - Tallinn, Estland Dauer: 31 Aug. 1998 → 3 Sept. 1998 |
Publikationsreihe
| Name | Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) |
|---|---|
| Band | 1482 |
| ISSN (Print) | 0302-9743 |
| ISSN (elektronisch) | 1611-3349 |
Abstract
Finite impulse-response filters (FIR filters) are very commonly used in digital signal processing applications and traditionally implemented using ASICs or DSP-processors. For FPGA implementation, due to the high throughput rate and large computational power required under real-time constraints, they are a challenging subject. Indeed, the limitation of resources on an FPGA, i. e., logic blocks and flip flops, and furthermore, the high routing delays, require compact implementations of the circuits. Hence, in lookup table-based FPGAs, e. g. Xilinx FPGAs, FIR-filters were implemented usually using distributed arithmetic. However, such filters can only be used where the filter coefficients are constant. In this paper, we present approaches for a more flexible FPGA implementation of FIR filters. Using pipelined multipliers which are carefully adapted to the underlying FPGA structure, our FIR filters do not require a predefinition of the filter coefficients. Combining pipelined multipliers and parallely distributed arithmetic results in different trade-offs between hardware cost and flexibility of the filters. We show that clock frequencies of up to 50 MHz are achievable using Xilinx XC40xx — 5 FPGAs.
ASJC Scopus Sachgebiete
- Mathematik (insg.)
- Theoretische Informatik
- Informatik (insg.)
- Allgemeine Computerwissenschaft
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Field-Programmable Logic and Applications: From FPGAs to Computing Paradigm - 8th International Workshop, FPL 1998, Proceedings. Hrsg. / Reiner W. Hartenstein; Andres Keevallik. Springer Verlag, 2006. S. 441-445 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Band 1482).
Publikation: Beitrag in Buch/Bericht/Sammelwerk/Konferenzband › Aufsatz in Konferenzband › Forschung › Peer-Review
}
TY - GEN
T1 - A flexible implementation of high-performance FIR filters on Xilinx FPGAs
AU - Do, Tien Toan
AU - Kropp, Holger
AU - Reuter, Carsten
AU - Pirsch, Peter
PY - 2006/5/27
Y1 - 2006/5/27
N2 - Finite impulse-response filters (FIR filters) are very commonly used in digital signal processing applications and traditionally implemented using ASICs or DSP-processors. For FPGA implementation, due to the high throughput rate and large computational power required under real-time constraints, they are a challenging subject. Indeed, the limitation of resources on an FPGA, i. e., logic blocks and flip flops, and furthermore, the high routing delays, require compact implementations of the circuits. Hence, in lookup table-based FPGAs, e. g. Xilinx FPGAs, FIR-filters were implemented usually using distributed arithmetic. However, such filters can only be used where the filter coefficients are constant. In this paper, we present approaches for a more flexible FPGA implementation of FIR filters. Using pipelined multipliers which are carefully adapted to the underlying FPGA structure, our FIR filters do not require a predefinition of the filter coefficients. Combining pipelined multipliers and parallely distributed arithmetic results in different trade-offs between hardware cost and flexibility of the filters. We show that clock frequencies of up to 50 MHz are achievable using Xilinx XC40xx — 5 FPGAs.
AB - Finite impulse-response filters (FIR filters) are very commonly used in digital signal processing applications and traditionally implemented using ASICs or DSP-processors. For FPGA implementation, due to the high throughput rate and large computational power required under real-time constraints, they are a challenging subject. Indeed, the limitation of resources on an FPGA, i. e., logic blocks and flip flops, and furthermore, the high routing delays, require compact implementations of the circuits. Hence, in lookup table-based FPGAs, e. g. Xilinx FPGAs, FIR-filters were implemented usually using distributed arithmetic. However, such filters can only be used where the filter coefficients are constant. In this paper, we present approaches for a more flexible FPGA implementation of FIR filters. Using pipelined multipliers which are carefully adapted to the underlying FPGA structure, our FIR filters do not require a predefinition of the filter coefficients. Combining pipelined multipliers and parallely distributed arithmetic results in different trade-offs between hardware cost and flexibility of the filters. We show that clock frequencies of up to 50 MHz are achievable using Xilinx XC40xx — 5 FPGAs.
UR - http://www.scopus.com/inward/record.url?scp=33845332789&partnerID=8YFLogxK
U2 - 10.1007/bfb0055277
DO - 10.1007/bfb0055277
M3 - Conference contribution
AN - SCOPUS:33845332789
SN - 3540649484
SN - 9783540649489
T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
SP - 441
EP - 445
BT - Field-Programmable Logic and Applications
A2 - Hartenstein, Reiner W.
A2 - Keevallik, Andres
PB - Springer Verlag
T2 - 8th International Workshop on Field-Programmable Logic and Applications, FPL 1998
Y2 - 31 August 1998 through 3 September 1998
ER -