Details
| Originalsprache | Englisch |
|---|---|
| Seiten (von - bis) | 563 - 573 |
| Seitenumfang | 11 |
| Fachzeitschrift | IEEE Journal of Solid-State Circuits |
| Jahrgang | 59 |
| Ausgabenummer | 2 |
| Frühes Online-Datum | 30 Jan. 2024 |
| Publikationsstatus | Veröffentlicht - Feb. 2024 |
Abstract
This article presents a dual-inductor ladder (DIL) hybrid buck converter to support system-on-chip (SoC)-compatible subvolt (<inline-formula> <tex-math notation="LaTeX">$\le$</tex-math> </inline-formula>1 V) supply rails directly from a single-cell Li-ion battery (2.5–5 V). Facilitating an extreme downconversion (16.67<inline-formula> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula>) using scaled CMOS technology, the proposed topology presents a unique solution to address the active versus passive component utilization while still neutralizing the well-known efficiency versus power density (PD) trade-off for a hybrid converter. The balanced inductor currents help reduce the average switch currents, improving active switch utilization, while the natural soft-charging of the flying capacitors reduces the switch rms currents, improving passive component utilization and PD. The DIL, thus, presents an optimal two-inductor solution for similar applications achieving excellent efficiency and PD. Fabricated in a 65 nm bulk CMOS technology, the DIL obtains 90.6% peak efficiency, 0.93 W/mm<inline-formula> <tex-math notation="LaTeX">$^2$</tex-math> </inline-formula> peak active PD (PPD) with a maximum power delivery of 1.35 W occupying just 1.13 mm<inline-formula> <tex-math notation="LaTeX">$^2$</tex-math> </inline-formula> die area.
ASJC Scopus Sachgebiete
- Ingenieurwesen (insg.)
- Elektrotechnik und Elektronik
Zitieren
- Standard
- Harvard
- Apa
- Vancouver
- BibTex
- RIS
in: IEEE Journal of Solid-State Circuits, Jahrgang 59, Nr. 2, 02.2024, S. 563 - 573.
Publikation: Beitrag in Fachzeitschrift › Artikel › Forschung › Peer-Review
}
TY - JOUR
T1 - A Dual-Inductor Ladder Buck Converter for Li-Ion Battery-Operated Sub-Volt SoCs
AU - Mishra, Arindam
AU - Zhu, Wei
AU - Wicht, Bernhard
AU - Smedt, Valentijn De
PY - 2024/2
Y1 - 2024/2
N2 - This article presents a dual-inductor ladder (DIL) hybrid buck converter to support system-on-chip (SoC)-compatible subvolt ( $\le$ 1 V) supply rails directly from a single-cell Li-ion battery (2.5–5 V). Facilitating an extreme downconversion (16.67 $\times$ ) using scaled CMOS technology, the proposed topology presents a unique solution to address the active versus passive component utilization while still neutralizing the well-known efficiency versus power density (PD) trade-off for a hybrid converter. The balanced inductor currents help reduce the average switch currents, improving active switch utilization, while the natural soft-charging of the flying capacitors reduces the switch rms currents, improving passive component utilization and PD. The DIL, thus, presents an optimal two-inductor solution for similar applications achieving excellent efficiency and PD. Fabricated in a 65 nm bulk CMOS technology, the DIL obtains 90.6% peak efficiency, 0.93 W/mm $^2$ peak active PD (PPD) with a maximum power delivery of 1.35 W occupying just 1.13 mm $^2$ die area.
AB - This article presents a dual-inductor ladder (DIL) hybrid buck converter to support system-on-chip (SoC)-compatible subvolt ( $\le$ 1 V) supply rails directly from a single-cell Li-ion battery (2.5–5 V). Facilitating an extreme downconversion (16.67 $\times$ ) using scaled CMOS technology, the proposed topology presents a unique solution to address the active versus passive component utilization while still neutralizing the well-known efficiency versus power density (PD) trade-off for a hybrid converter. The balanced inductor currents help reduce the average switch currents, improving active switch utilization, while the natural soft-charging of the flying capacitors reduces the switch rms currents, improving passive component utilization and PD. The DIL, thus, presents an optimal two-inductor solution for similar applications achieving excellent efficiency and PD. Fabricated in a 65 nm bulk CMOS technology, the DIL obtains 90.6% peak efficiency, 0.93 W/mm $^2$ peak active PD (PPD) with a maximum power delivery of 1.35 W occupying just 1.13 mm $^2$ die area.
KW - Buck converter
KW - Buck converters
KW - CMOS technology
KW - Capacitors
KW - Electronics packaging
KW - Inductors
KW - Li-ion battery
KW - Topology
KW - Voltage
KW - dc–dc converter
KW - hybrid converter
KW - soft-charging
KW - switched-capacitor (SC) converter
KW - dc converter
KW - dc
UR - http://www.scopus.com/inward/record.url?scp=85174850120&partnerID=8YFLogxK
U2 - 10.1109/jssc.2023.3313963
DO - 10.1109/jssc.2023.3313963
M3 - Article
VL - 59
SP - 563
EP - 573
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
SN - 0018-9200
IS - 2
ER -